面向软件定义无线电的射频集成电路片上自适应校准关键技术研究

Software-Defined Radio Frequency Integrated Circuits (SDRFICs) are highly configurable and form the basis of common hardware platform for the information society in the future. Current SDRFICs show poor robustness against static non-ideal factors such as process variations, device mismatch, and dynamic non-ideal factors such as changes of temperature, gain and input frequency, also not have the capability of self-adaptive calibration. This project deeply study the key factors that affect the performance of SDRFICs. Through the establishment of dynamic tracking mechanism, the process-temperature compensation mechanism of resistor and capacitor and the mapping look-up mechanism, the necessary on-chip self-adaptive calibration algorithms and the corresponding specific circuits are analyzed and designed, which include I/Q mismatch calibration, DC offset calibration, wideband filter bandwidth calibration, harmonic distortion calibration and wideband frequency synthesizer stability calibration, to greatly enhance the robustness of SDRFICs. The research results can provide theoretical and practical support for the realization of high performance SDRFICs.

软件定义无线电射频集成电路具有极强的可配置性，是未来信息社会的基础通用型硬件平台。当前的软件定义无线电射频集成电路针对工艺偏差、器件失配等静态非理想因素以及温度变化、增益改变、输入频率变动等动态非理想因素所表现出的鲁棒性较差，且不具备自适应校准能力。本项目深入挖掘影响软件定义无线电射频集成电路性能的关键因素，通过建立动态跟踪机制、电阻电容的工艺温度补偿机制以及映射查找机制，对必要的片上自适应校准算法和对应的具体电路展开分析和设计，具体包括I/Q通路失配校准、直流偏移校准、宽带滤波器带宽校准、谐波失真校准以及宽带频率综合器稳定性校准，大大提升软件定义无线电射频集成电路的鲁棒性。研究成果可为高性能软件定义无线电射频集成电路的实现提供理论和实践支撑。

软件定义无线电射频集成电路具有极强的可配置性，是未来信息社会的基础通用型硬件平台。本项目深入挖掘影响软件定义无线电射频集成电路性能的关键因素，对必要的片上自适应校准算法和对应的具体电路展开分析和设计，针对宽带射频收发链路、宽带频率综合器、多通道射频收发同步需求等3个典型应用场景，共计提供了11种校准技术的完整解决方案，并针对软件定义无线电应用场景中的超宽带低噪声放大器、谐波抑制混频器等提供了详细的解决方案。研究成果可为高性能软件定义无线电射频集成电路的实现提供理论和实践支撑。