效能驱动的光互连视频阵列处理器动态自重构体系结构

With the endless emerging of new applications and new algorithms, such as ultra high definition video codec, computer vision, etc., the amount of computations and power consumptions increases rapidly, so there is a pressing need for a innovative computing architecture, which takes account of computational efficiency and programmable flexibility. Firstly, facing the diversification of video application scenario, according to the problems such as lack of flexibility, low resource utilization and difficulty of performance improvement of CGRAs and other reconfigurable architectures, this project explores the productivity-driven dynamic self-reconfigurable mechanism based on a massive thin-core array structure with three-dimensional (3D) adjacent addressing and it focuses on the new method of "hardware reconfiguration" by "software programming" in video processor. Secondly, for the high-performance requirements of intra-PE and inter-PE interconnecting in self-reconfigurable arrays, this project tries to propose a new 3D integrated topology of local electric cross-interconnection and global multi-ring nested interconnection in order to solve the communication wall issue. Finally, the team attempts to establish a distributed shared on-chip storage architecture with unified addressing for solving the problem of efficient access to mass data and configuration information of video processor. This project expects to break through the new technologies such as dynamic programmable self-reconfiguration and 3D photoelectric hybrid interconnection, and establishes the video array processing architecture and prototype system which adapt to the development of nanometer-technology with both the flexibility of software programming and the high performance of special hardware calculation, and provides a beneficial reference which can break through the bottleneck of the development of the processor architecture in the post Moore Era.

超高清视频编解码、计算机视觉等新应用、新算法层出不穷，计算量迅速飙升，功耗不断激增，急需兼顾计算高效性和应用灵活性的新型体系结构。首先，面向视频应用的多样化场景，针对CGRAs等重构结构灵活性不足、资源利用率低、性能提升困难等问题，基于三维邻接寻址的大规模轻核阵列结构，探索效能驱动的动态自重构机制。重点研究视频处理器通过“软件编程”动态实现“硬件重构”的新方法。其次，针对自重构阵列中PE内和PE间的高性能互连需求，尝试提出局部电交叉互连全局光多环嵌套互连的新型三维拓扑结构，解决“通信墙”问题。最后，着手建立统一寻址的分布式共享片上存储结构，解决视频处理器海量数据和配置信息的高效存取问题。预期突破可编程动态自重构、三维光电混合互连等新技术，建立适应纳米工艺发展的视频阵列处理体系结构及其原型系统，兼有软件编程的灵活性和专用硬件计算的高性能，为突破后摩尔时代处理器体系结构的效能瓶颈提供有益参考。

项目面向超高清视频编解码、计算机视觉等层出不穷的新应用、新算法，以及迅速飙升的计算量和不断激增的功耗，研究并提出了一种兼顾计算高效性和应用灵活性的新型体系结构——效能驱动可编程自重构的光互连视频阵列处理器体系结构（APR）。.首先，提出了一种根据实际应用中处理元（PE）运行状态进行阵列处理器功能重构的动态自重构机制HRM。HRM是基于H树的层次化重构机制，由重构控制器对阵列执行状态，包括忙闲状态、执行指令次数、访存频次、邻接数据交互等进行实时监测，并通过H树配置网络高效下发阵列处理器的配置指令。.其次，构建了基于邻接互连的数据流与指令流双模驱动的轻核处理元阵列结构APR。轻核处理元的双模驱动兼顾了灵活性与高效性，并通过邻接寄存器增强了扩展性；APR中处理元以4x4形式构成逻辑簇，可支持1到64个逻辑簇，可从16扩展到1024个处理元。.第三，提出了一种局部电互连全局光互连的自适应光电混合互连分流结构。该结构底层为电网络层，上层为光网络层，层间通过硅通孔协同电路由器来控制光链路的建立、响应和撤销，充分利用边缘路由节点的未用端口配置微环谐振器，实现数据分流，无阻塞地完成数据的可靠通信。.第四，提出了一种统一编址的分布式共享存储结构。分布式Cache结构“物理分布、逻辑统一”，通过创新存储数据的动态迁移机制，将原本映射于固定Cache块的数据迁移至邻近处理元的Cache块中，实现存储访问的低延迟、高带宽、高并行度。.最后，为验证项目的创新内容，基于BEE4的FPGA开发板搭建了APR原型系统，系统工作频率为156MHz，可以实现HEVC标准的视频编解码；同时，采用SMIC 55nm CMOS工艺完成了芯片设计，片上集成了16个处理元和6MB的SRAM，最高工作频率为180MHz，已通过MPW进行流片，可支持分辨率为1024x768的HEVC视频编解码。.项目研究成果为突破后摩尔时代处理器体系结构瓶颈提供了有益参考。