可重构多核处理器设计方法及其关键技术研究

With the increasing complexity and capacity of computing in embedded systems, Chip Multi-processor(CMP) system is gradually replacing the single processor-based SoC system as the next-generation development mainstream. Meanwhile, the interconnects among the on-chip processor cores of CMP are becoming more and more important, and Network-on-Chip (NoC) is a promising solution for the interconnection of CMP because of its excellent parallelism,scalability,and high communication efficiency. However, NoC will consume extra energy which can be a serious concern especially when more cores are connected in a CMP along with the technology scaling. Adopting CMP in embedded systems, especially for mobile computing applications, requires low-power design. One promising technique is to design the CMP with reconfigurable interconnects in such a way that its on-chip computing resources can be turned on and off dynamically to save energy..In this proposal, we will focus on the key technologies and their basic theories of the reconfigurable CMP design, including reconfigurable routing and switching circuit design,shared memory allocation and consistency management,and fault-tolerance of race conditions. Gaussian Integer, Markov Chain, and Probability Distribution will be introduced to analyze the critical problems on reconfigurable routing of CMP interconnects, probability of instruction transitions for memory allocation, and the normalized distribution of timing delay for fault-tolerant design. Meanwhile, new circuits of routing switches, buffer allocation and delay compensation will be proposed and designed for system integration of CMP. .The expected results include the following items: 1) New design models of reconfigurable CMP based on Gaussian network will be presented; they form the foundation of the optimization algorithms for the shortest path routing using the Gaussian distance, and the switch circuitry can be designed for interconnects to meet the reconfiguration and optimal routing requirements.2) New multi-task analysis methods based on Markov chain will be presented to show the transition probability of the instructions processing and data calling in multi-task programs; these methods make it possible to allocate cache dynamically and manage shared memory in consistency. 3) Normalized distribution of package switching delay and circuit timing variation will be presented to model time-events of programs running with dynamic reconfiguration, and the graph of race condition about scheduling conflict of CMP system is given as a quantitative analytical tool for the design of pipeline-based circuits with fault-tolerance for CMP ensuring design reliability. 4) FPGAs will be used to implement a CMP system integrating 64 Leon3 processors with reconfigurable interconnects; it will be dynamically configured for memory allocation and experiment with different on-chip resources running different tasks.

片上多核处理器(CMP)之间通讯要求其互联结构具备高的吞吐率和低的延迟特性，同时鉴于CMP芯片将来在嵌入式系统及移动计算中的实际应用还要求其低功耗设计，因此还得考虑CMP片上互联具备可重构特性，以支持片上网络及其计算资源具备动态开启功能。就设计可重构CMP芯片所涉及到的技术基础问题，本项目主要研究：1）建立支持网络拓扑自动构造的数学模型，设计满足CMP片上网络拓扑可重构要求的路由交换结构和电路实现方案；2）设计适用于可重构互联的 CMP多级缓存动态分配方案及其共享内存的一致性管理机制，提高片上内存使用率；3）分析不同拓扑配置下CMP各处理器间通讯时延与电路时序延迟的统计特性，设计基于竞态条件分析方法解决时序冲突与系统容错的流水线结构电路，提高CMP应用系统的可靠性。最后，利用FPGA搭建一款集成64个Leon3处理器的可重构CMP应用验证系统，为实际设计可重构CMP芯片奠定技术研究基础。

随着移动计算在应用终端的需求不断增加, 片上多核处理器已成为近年来人们开发和应用的重要研究对象. 片上多核处理器设计的关键在于片上网络交换路由、缓存共享和计算可重构方面的理论方法与芯片应用及应用系统可靠性技术等方面的研究。. 本课题研究内容主要以申请立项内容为基础，具体涉及: 1、片上网络路由交换节点的电路设计及其多核系统可重构网络数学建模; 2、片上网络多核系统的内存一致性协议设计及其系统可靠性分析；3、分布式及可重构计算在云存储共享安全及基因芯片大数据分析方面的应用设计与算法模型研究。. 主要研究成果体现在：1、基于Sparc处理器及其AMBA总线接口设计了一种集成包交换与线路交换的混合交换片上网络路由电路，该路由电路可以实现大规模多核（或众核）系统片上网络的可重构设置，并以高斯网络数学模型为基础建立可重构片上网络的路由模型；2、设计实现片上系统处理器的动态缓存电路结构，提升了片上系统计算有效性，并以混合交换片上网络为基础实现内存一致性管理协议，根据系统运行竞态条件建立可重构片上网络系统可靠性分析模型，证明了所设计的混合交换片上网络系统具备更好的系统可靠性；3、针对大计算量的云存储共享安全及基因芯片数据分析，基于分布式计算及并行计算原理，设计了以双曲线对为加解密算法的并行计算实现电路及数据存储安全共享协议，给出高维数据特征提取与特征分类的高效计算方法，分析获得了可以描述基因调控网络可重构计算模型。. 其中，算法理论方面的研究成果基本以学术论文发表，已发表学术论文50多篇(多数被SCI/EI收录)，特别是在本课题领域国际专业刊物如IEEE Trans. on Computer、IEEE Trans. on VLSI、J. of Parallel and Distributed Computing等刊物上发表数篇有影响的论文；同时，开发出几种可复用设计的片上网络及多核系统与加解密应用的IP核和SoC芯片方案，相应的创新技术也已申请国家发明专利，并设计相应的软件，还培养了6名博士生和25名硕士生。. 总之，本项目课题基本按计划完成，所获得成果可以为可重构片上网路系统设计与应用提供重要的理论基础和技术参考。