无线片上网络高可靠通信关键技术研究

Wireless network-on-chip is a new on-chip multi-core interconnect paradigm. Crosstalk and circuit aging are main factors leading to failure of circuit components and network congestion, which can seriously impact the communication efficiency and reliability of wireless network-on-chip. Serving as the critical routing nodes in network, if wireless routers occur fault or congestion, the network communication efficiency can be even more severely affected. In this study, fault tolerance and congestion avoidance strategies will be applied to establish a guaranteed mechanism for on-chip high reliability communication. Firstly, a hybrid e2e and s2s retransmission mechanism for wireless on-chip network will be explored to achieve low-cost fault tolerance for the instantaneous failures of the links and on-chip components in the network. In addition, a temporary passthrough and fault awareness permanent fault tolerance scheme will be designed to improve the overall network communication efficiency. Furthermore, a wireless node-level congestion avoidance mechanism will be proposed to reduce packets transmit to the congested wireless nodes. Finally, a wireless link-level congestion avoidance mechanism is presented to achieve lower competition frequency of wireless link and hence improve communication reliability of upper-layer wireless networks. This study aims at improving the communication reliability of the chip through the fault tolerance and congestion avoidance designs of wireless on-chip network. Through the fault tolerance and congestion avoidance designs of wireless on-chip network, the communication reliability of the chip can be effectively improved and the theory of the integrated circuit design enriched, which also provides the key technical support for the high reliable communication of the integrated circuit.

无线片上网络是一种新型的片上多核互连技术。由于串扰、电路老化等因素的影响，芯片内部易出现故障或通信不畅等问题，严重影响片上网络的通信效率和可靠性。无线节点是无线片上网络数据通信的关键节点，若出现故障或拥塞问题，其影响将会更加恶劣。本课题拟运用故障容错与拥塞避免策略，构建无线片上网络高可靠通信的保证机制。首先，探索一种适用于无线片上网络的混合e2e与s2s重传机制，对片上链路和元器件出现的瞬时性故障，实现低开销容错。其次，设计一种临时直通与故障感知的永久性故障容错机制，提高整个网络的通信效率。再次，提出一种无线节点级拥塞避免机制，减少向已经拥塞的无线节点广播数据包。最后，提出一种无线链路级拥塞避免机制，降低无线链路的竞争频率，实现上层无线网络的高可靠通信。本课题拟对无线片上网络运用故障容错和拥塞避免设计，提高芯片的通信可靠性，丰富和发展集成电路设计理论，为集成电路高可靠通信提供关键技术。

在传统片上网络架构中引入毫米波通讯技术能够极大地缓解通讯组件的拥塞问题，但同时更加复杂的硬件构造和连线也对芯片的可靠性带来的新的挑战。受串扰、老化等因素的影响，芯片内部会出现故障和通信不畅等问题，影响片上网络的通讯效率与可靠性。无线节点由于更复杂的构造和承担更高的负载，更容易出现拥塞和故障，同时无线节点故障所带来的影响往往更加恶劣。为了提升芯片可靠性，本课题从故障容错与拥塞避免策略入手，在容忍上层无线网络的瞬时性故障和永久性故障、缓解上层网络无线节点级拥塞和无线链路级拥塞等方面取得了创新型成果：.1）提出一种混合e2e与s2s的低开销重传机制。以低开销方式缓解片上网络中瞬时性故障导致的数据错误，提升重传数据传输效率。.2）提出一种临时直通与故障感知的永久性故障容错机制。针对网络中的永久性故障节点设计直通路径，保证数据传输正常进行。.3）提出一种无线节点级拥塞感知与避免机制。大幅度缓解无线节点及周边拥塞，均衡网络负载。.4）提出一种基于并行FIFO的无线链路级拥塞避免机制。增加单周期内无线链路的数据吞吐率，降低无线链路的竞争频率，提升网络整体性能。.5）提出一种作用于torus网络的死锁避免方案。通过中转环的设计消除气泡流控因死锁控制导致的环间通讯低效问题，大幅度提升网络吞吐量。.6）在Journal of Parallel and Distributed Computing、IEEE Asian TEST SYMPOSIUM (ATS)、The Journal of Supercomputing、INTEGRATION, the VLSI journal、Journal of Electronic Testing 、Tsinghua Science and Technology、电子学报、仪器仪表学报等国内外著名期刊和会议上发表学术论文31篇（SCI、EI收录26篇）；授权发明专利6件；培养出12名硕士。.本课题建立了系统的无线片上网络通讯模型，从故障容忍和拥塞避免两个方面入手，设计了高可靠通讯的保证机制。本课题的相关研究成果，为无线片上网络通信高可靠通讯和集成电路通讯架构优化等方面的进一步研究和实践，提供了参考和借鉴。