基于冗余数系统的高能效近似逻辑电路设计技术研究

Energy-efficient chip design has always been an important research topic, and challenged with the continuous development of semiconductor technologies, and their extensive applications in the fields of biomedical, energy harvesting, and mobile computing. Energy efficiency imposes a key constraint on the design, which aims to minimize the energy consumption with the targeted performance, or alternatively speaking, to maximize the speed with limited energy budget. Approximate computation cooperates with the low voltage design techniques provide a possibility to improve energy efficiency in error resilient applications at the cost of reduced computation accuracy. In this project, we shall begin with an analysis on a revised energy-delay model for a specific nanometer technology. Several approximate algorithms are proposed and examined in a redundant binary representation. With the exploration on the tradeoffs among the key metrics, such as supply voltage, circuit delay, computation accuracy, and error probabilities, a comprehensive study on the energy efficiency shall be carried out from three dimensions, which includes the energy, the delay, and the precision as well. In the meanwhile, redundant number system is also utilized for the circuit design due to its carry-free property. Different coding methods are explored with various approximate logic implementations, and each of which will be studied extensively, giving rise to the coding efficiency analysis. At the end, a digital filter or an FFT processor will be taken as design vehicles to illustrate this design approach. The figure of merit for both silicon-validated circuits will be analyzed and evaluated. This study may enlighten the research in the future for the high energy-efficient digital circuits design in the nanometer scale era.

高能效芯片设计一直以来都是集成电路设计领域的一个重要课题及挑战，特别是近年来随着移动计算、能量采集、生物医疗等应用的兴起和普及，芯片的能效性成为直接影响其设计方案成功与否的关键。如何在满足芯片性能约束的条件下最小化其能耗，或是在满足能耗需求的情况下最大化其性能，是高能效电路设计中所关注的核心问题。基于容错设计的近似计算通过不精确的硬件设计实现其近似的逻辑功能，与低压设计技术相结合有望成为提高电路能效性的一个重要途径。本课题拟从一般的能量-延时积模型入手，加入近似计算下的误差分析和精度控制，从延时、能量、精度三个维度上对电路的能效性进行更有效地分析和评估，以此建立起基于近似计算的高能效电路设计理论；同时利用冗余数制不产生进位的优势，通过高效编码方式进行电路优化，在冗余数系统下解决高能效电路的实现问题。本课题的研究旨在为纳米工艺下高能效数字集成电路设计提供一种可借鉴的解决思路。

如何提高芯片的能量效率一直以来都是IC设计领域一个重要的课题及挑战，特别是随着大数据处理、移动计算、生物医疗等应用的兴起和普及，电路能效性更是成为影响芯片设计方案成功与否的关键。本项目研究高能效近似逻辑电路设计技术及其在集成电路设计领域的实现问题，依次从理论模型，设计方法，逻辑单元，功能模块，以及电路系统这几方面展开研究，对如何实现高能效数字集成电路设计提供一种可借鉴的解决思路。本项目主要完成的内容包括以下四个方面：1.提出基于近似计算的EDAP模型，建立起新的高能效电路设计理论；2.提出一种基于Booth编码的概率预测近似技术用于高能效数据通路的设计与实现；3.基于近似逻辑单元电路的设计思路，提出近似逻辑单元的设计方案及其电路实现方法，用于可容错运算中；4.根据离散余弦变换器的可容错性，提出基于冗余数制CSD编码的近似算法，并完成该DCT芯片的设计和验证。本项目在实施过程中共计培养博士生1名，硕士生9名(包括1名转硕博连读)，发表学术论文10篇，学术专著1部，申请13项中国发明专利，其中4项已获授权，完成预期目标。