10+GS/s超高速逐次逼近型模数转换器关键技术研究

Ultra-high-speed analog to digital converters (ADC) are the key modules in optical communication systems and millimeter wave radars. The sampling rate and conversion resolution of the ADC impact the performance of the whole system seriously. Related products and frontier theory of 10+GS/s ADCs are monopolized by the developed countries for decades. Domestic research level is still relatively backward. Therefore, to carry out the research on high-speed ADCs is significant and urgent. This project study deeply on system architecture and optimization technique of ultra-high-speed successive approximation register (SAR) ADC based on nanoscale CMOS technology. We break through the analog front-end sampling, multi-phase clock management, low-power sub-circuit modules, channel mismatch calibration, etc. We propose integrated time-interleaved SAR ADC implementation scheme and digital calibration to improve the performance. In addition, we will complete the verification of novel circuits and calibration algorithm. This project develops ultra-high-speed ADC for the application of millimeter wave radars and next generation optical communication systems.

超高速A/D转换器是光通信、毫米波雷达等系统的关键芯片模块，其采样速度和精度严重影响着整个系统的性能。对于10GS/s以上采样率的A/D转换器，相关产品及前沿理论长期被发达国家垄断，国内研究水平仍相对落后。因此，开展超高速A/D转换器技术研究是十分重要且迫切的。本项目基于纳米级CMOS工艺，深入研究超高速逐次逼近型A/D转换器系统结构和优化技术，突破模拟前端采样、多相位时钟管理、低功耗子电路模块、通道失配校准等关键技术，提出单片集成的时域交织逐次逼近型A/D转换器芯片整体实现方案，并结合数字校准电路对整体性能进行优化，完成新型电路结构及校准算法验证，为后续超高速A/D转换器研发及其在毫米波雷达、下一代光通信等系统中的应用奠定基础。

超高速模数转换器是光通信、毫米波雷达等系统的关键芯片模块，其采样速度和精度严重影响着整个系统的性能。本项目研究超高速逐次逼近型模数转换器架构及电路技术。首先研究了多级模拟前端采样及通道失配校准技术，提出了32GS/s多级前端采样模型并分析了带宽和效率间的折中。提出了消除时钟偏差的二阶补偿技术，在后台对误码进行提取和补偿，达到快速收敛、高校准精度的效果，完成了10位两通道时域交织逐次逼近型模数转换器校准算法验证。其次研究了高速子通道逐次逼近型模数转换器，突破了一步多位关键技术，实现子通道采样率大幅提升，流片实现了7位900MS/s一步三位逐次逼近型模数转换器、8位350MS/s一步1.5位逐次逼近型模数转换器等。依托本项目共发表SCI论文12篇。本项目研究成果可有效提高逐次逼近型模数转换器采样率，降低其在时域交织结构中的校准复杂度，并提高整体能效比，对超高速模数转换器发展具有促进作用。