面向物联网感知层低功耗可靠通信的超低存储容量译码结构设计及实现

To deal with the contradiction between computing, energy resource constraints and reliable data transmission in the perception layer of IoT, the powerful error correction code, i.e. the Turbo code, is applied to the perception layer in the research of this project. Based on the design of state metrics cache (SMC) reduced low-power decoding architecture, this project aims to achieve energy-efficient multi-hop relay technologies. By decomposing the trellis diagram of Turbo code, the approximated asymmetrical max* operator pair and the corresponding reverse calculation are modeled for a new decoding algorithm, in which the bit error rate and the decoding complexity are unified under the low-power decoding architecture design strategy. Furthermore, by replacing the state metrics with register flag bit and inserting reverse calculation module, the SMC size is reduced by 95%. Based on FPGA, This research applies the ultra-low SMC storage decoding architecture to construct the nodes of perception layer, and two kinds of multi-hop relay schemes are specified for energy-efficient data retransmission. The research of this project is expected to reveal that, by adopting the approximated asymmetrical max* operator pair decoding algorithm and the ultra-low SMC storage decoding architecture, near optimal decoding performance and improved life cycle for the nodes of perception layer can be achieved. As a whole, this research intends to provide scientific basis and hardware verification platform for low-power dissipation and reliable communication in the perception layer of IoT.

针对物联网感知层节点计算资源、电源资源受限与数据传输可靠性之间的矛盾，本项目将具有强大纠错能力的Turbo码应用于感知层，以降低状态度量缓存(State Metrics Cache: SMC)容量的译码结构设计为基础，实现低功耗的高效多跳转发技术。通过分解译码网格图，构造非对称max*成对近似与反向计算的译码算法，使得误码率、译码复杂度在低功耗译码结构设计策略下得到了统一；采用标志寄存器位代替状态度量值存储策略和嵌入反向计算模块的方式，将SMC容量降低了95%；将超低存储容量的Turbo码译码结构，用于构造基于FPGA的感知层传感节点，提出了两种降低数据帧重发功耗的多跳转发技术；项目预期将揭示在非对称max*成对近似的译码算法和超低SMC容量的结构设计方式下，能获得接近最优译码算法的性能，提高感知层节点生命周期，为物联网感知层的低功耗可靠通信提供科学依据和硬件验证平台。

无线传感器网络在现代社会中具有广泛的应用前景。在能量受限的场合，数据传输可靠性和功率消耗是一对矛盾。本项目首先研究了低功耗的Turbo码译码器结构设计方案，以降低存储容量为策略，提出了对状态度量值反向计算、循环压缩和标志位的三种设计方案，将存储容量降低了50%、53%和65%。通过FPGA硬件实现和功耗测试，证实了研究方案的有效性和可行性，研究成果可直接用于低功耗的Turbo码译码器实现。在工业4.0中的高性能工业控制场合，无线传感器网络的高可靠性和低时延也是一对矛盾。本项目参与了一种全新工业无线通信方案物理层协议的研制，设计了该物理层协议数据传输的信道编码方案。利用通用无线电外设在实际工厂环境下的测试，详细研究了不同编码方案的可靠性、不同调制方案下的传输效率，以及抗脉冲干扰性能，表明在工厂环境下能够达到10e-7误包率，论证了信道编码在该通信协议物理层中的有效性，为本领域的研究提供了一整套研究策略和测试方法。在本项目的支持下，建立起了基于FPGA的信道编码译码器结构硬件测试平台，进一步扩展到系统级研究，建立起了基于通用无线电外设的无线传感器网络综合性能测试平台。本项目研究取得了一系列较高质量的成果，培养了10名硕士研究生，为课题组的后续发展打下了坚实的基础。