低电压数字辅助型电荷域流水线ADC关键技术研究

The charge-domain (CD) pipelined analog-to-digital converter (ADC) is a novel high speed low power A/D conversion technique without using high gain opamps. However, due to the signal swing restriction of the boosted charge transfer (BCT) circuit used in this novel ADC, it fails to work under low voltage conditions. Moreover, its precision suffers from the conversion errors caused by the charge transfer nonlinearity of BCTs and the capacitors mismatches of each sub-stage. Based on the research results of a series of projects during the 12th Five-Year Plan Period, this project will make further research in the BCT circuit structures and the digital calibration methods of the key conversion errors for the CD ADCs in low voltage conditions. For the signal swing restriction problem of BCTs, this project will firstly analyze the mechanism of the signal swing restriction of BCTs, then adopt both the negative voltage buck and the bootstrapped methods to increase the signal swing for the BCTs. For the charge transfer nonlinearity of BCTs and the capacitors mismatches of each sub-stage, this project will firstly build a mathematical model of the nonlinearity of BCTs and analyze the mechanism of the capacitors mismatches in each sub-stage, then explore a background and a foreground digital calibration methods respectively to compensate the errors caused by the charge transfer nonlinearity of BCTs and the capacitors mismatches of each sub-stage. This project is a basic research on application, which has a significant value on embedding the high speed, high precision pipelined ADCs in the nanometer CMOS platform.

电荷域流水线模数转换器(ADC)是一种不使用高增益运放的新型高速、低功耗A/D 转换技术。然而，这种ADC受其使用的增强型电荷传输(BCT)电路信号摆幅限制而无法在低电压下工作，并且其精度受BCT电荷传输非线性和各子级电容失配误差的限制。本项目在“十二五”期间一系列项目的研究基础上，进一步研究电荷域ADC在低电压条件下所需要的BCT电路结构和针对电荷域ADC关键转换误差的数字校准技术。针对BCT信号摆幅问题，首先进行BCT信号摆幅机理分析，然后采用负电压降压和栅自举升压两种方法，增大BCT信号摆幅。针对BCT电荷传输非线性和各子级电容失配误差，首先进行BCT电荷传输非线性的数学建模和各子级电容失配的机理分析，然后分别运用数字后台和前台两种方法对BCT电荷传输非线性和各子级电容失配误差进行补偿。本项目属于应用基础研究，对于实现高速高精度流水线ADC在纳米级工艺平台上的嵌入式应用具有重要意义。

本项目对电荷域ADC在低电压条件下所需要的增强型电荷传输(BCT)电路结构和关键转换误差的数字校准技术进行了深入的理论分析。在此基础上，采用负电压降压和栅自举升压两种方法提升BCT信号摆幅，并完成了2种大摆幅BCT电路结构研究，可有效解决现有电荷域ADC输入信号摆幅不足的缺陷；分别运用数字后台和前台两种校准方法对BCT电荷传输非线性和各子级电容失配误差进行补偿，完成了同时采用前台和后台方法的数模混合校准技术研究，解决了该校准方法系统到电路各个层次的一系列关键技术问题，该混合校准技术不仅可以完成电荷域流水线ADC的误差校准，还可以应用于通用数模混合电路误差校准中，具备实时校准以及对外界干扰不敏感等特性。.项目组在本项目研究成果的基础上，首先基于0.18um CMOS工艺，设计了一款时间交织14位500MSPS电荷域流水线ADC芯片并流片测试，该ADC信噪比达70dB，无杂散动态范围达82dB，功耗仅为460mW；另外，基于采用65nm CMOS工艺，设计了一款单核14位1GSPS电荷域流水线ADC芯片并流片测试，该ADC信噪比达65dB，无杂散动态范围达78dB，功耗为960mW；此外，还将本项目所研究数模混合校准技术成功应用于14位、时钟频率达2.5GHz的DAC电路中进行误差校准。 .本项目的部分研究进展已经在Analog Integrated Circuits and Signal Processing、Chinese Journal of Electronics、Tsinghua Science and Technology、电子与信息学报、西安电子科技大学学报等期刊和多个IEEE国际会议上发表论文9篇，申请中国发明专利8项（4项已授权）、美国专利1项；培养中青年学术带头人2人。