功率模块的多维度结构材料实现及功能集成

In order to reduce energy consumption of the power device and to increase the capacity, it is usually required the use of a thick epitaxial layer of 100 to 200 micrometers as the device drift layer, and a corresponding high-energy ion implantation at high temperature and annealing at high temperature to complete the production of the device. These requirements increase the difficulty of making power device with high voltage resistance. In this project we propose the use of the multi-dimensional and the micro-nano methods to prepare devices with MOS structure and/or Schottky structure and their integration via one-run epitaxial growth. We grow in sequence the semi-insulating barrier layer, P+, N+ metal contact area, N- drift region and the P-type micro-nano block area by chemical vapor deposition. We propose to achieve multi-dimensional and micro-nano controlled epitaxial growth through the study of micro-nano epitaxial interface control and the suppress of the gas flow field. The innovations of this project are expressed as follows: lateral embodied structures are adopted in the devices, so the voltage resistance is proportional to the width of the N- drift layer which prevents the growth-limiting of the epitaxial layer thickness and prevents the preparation of P well in the N- drift layer. This avoids the compensation effect of the channel layer, thus improving the electron mobility of n channel, reducing the on-resistance of the device. So that reliable epitaxial structural materials used for the power devices with high voltage, high current and low on-resistance can be prepared. This project will be particular useful and lays a solid foundation to high-voltage silicon carbide power devices and its integration.

为了降低功率器件能耗、提高功率容量，通常需要采用厚达100~200微米的外延层为器件工作层，并且需要通过高温高能离子注入及相应的高温退火完成器件制作，这些要求增大了耐高压器件的制作难度。本研究提出采用多维度微纳外延的思路针对具有肖特基二极管和MOS结构的器件及其集成化生长进行研究，采用化学气相沉积方法同质外延生长高阻半绝缘隔离层、P+、N+金属接触区、N-漂移区以及P型微纳阻断区，通过研究外延界面控制以及微纳气流场的钳制，实现多维度的微纳可控外延生长。本研究创新点体现器件采用侧向结构，其耐压与N-漂移层宽度成正比，避免了生长厚外延层的限制；防止在N-漂移层上制备P阱，避免了沟道层的补偿效应，从而提高了n沟道的电子迁移率、降低了器件开态电阻，从而可靠地制备出耐高压大电流、低导通电阻的外延结构材料。本研究将对特别是碳化硅材料的高耐压功率器件及其集成化实现打下坚实基础。

碳化硅（SiC）是具有高的禁带宽度的第三代半导体材料，具有许多优良的性质，如抗电压击穿能力强、高电子饱和速度和电子迁移率、高热导率、低介电常数、抗辐射能力强，以及机械性能良好等,是适合制作大功率、高频率、高温、高压以及耐辐照器件的理想材料。研究提出采用多维度微纳外延的思路针对具有肖特基二极管和MOS结构的器件及其集成化生长进行研究，器件采用侧向结构，实现沟道载流子浓度1×1015 cm-3~1×1017 cm-3可调，迁移率大于200cm2/Vs其耐压与侧向外延层宽度成正比，避免了生长厚外延层的限制。进一步提高器件性能，实现静态耐压600 V/1.7 KV/3.3 KV，开态电阻小于50 mΩcm2，工作频率大于10 KHz。将对特别是碳化硅材料的高耐压功率器件及其集成化实现打下坚实基础。