面向高密度NAND闪存的高效纠错码与信号处理理论及技术研究

The performance of portable electronic devices,computing servers, and storage systems has been greatly improved by employing the high-density NAND flash memory. However, with the scaling-down of the CMOS process technology and the increase of the storage states per cell,the high-density NAND flash memory encounters several major challenges, such as the lowered storage reliability, the increased access delay and the reduced program/erase cycles. Such challenges call for immediate solutions. This project aims to address these challenges from the viewpoint of communication system, and carries on the following research topics: 1) Model high-density NAND flash memory channel based on the test platform of high -density NAND flash memory, probability theory and stochastic processes, determine the relationship between the noises and the parameters of the channel model. Such accurate channel model will provide fundamental basis for the study of channel detection and coding; 2) Design correlated threshold detection algorithm for the high-density NAND flash memory channel based on the rank modulation and previous obtained channel model. This will help to reduce access delay, slowing program/erase frequency and enlarge service life of the high-density NAND flash memory; 3)Optimize degree distributions of binary and non-binary LDPC codes through jointing channel detection, Construct structural LDPC codes with the help of protograph and ACE algorithm. This aims to further increase the storage reliability of high-density NAND flash memory; 4) Design and optimize the high efficient storage codes and channel detection scheme. This project will enrich the theory and technology of coding and signal processing on the non-volatile memory.

高密度NAND闪存的应用大幅提升了便携式电子设备、运算服务器以及存储系统的性能。但随着半导体制程尺寸的进一步缩小、单元存储状态的不断增加，迫切需要解决高密度NAND闪存面临的存储可靠性低、访问时延长、使用寿命短等关键问题。本课题拟从以下几方面开展针对性研究：1）基于高密度NAND闪存的信道测试平台，结合概率论与随机过程进行高密度NAND闪存信道建模，明确干扰噪声与信道模型参数之间的关系，为信道检测和编码设计提供基础；2）采用阶梯调制，结合信道模型，进行高密度NAND闪存信道关联门限检测算法的研究，从而达到缩短访问时延、降低编程/擦除频率、延长使用寿命的目的；3）联合信道检测，进行二元和多元LDPC码的度优化，并借助原模图和ACE算法，设计结构化LDPC码，提高存储靠可性；4）设计及优化高效存储编码与信道检测方案。本课题的研究将有助于丰富面向非易失数据存储领域的差错控制与信号处理理论及技术。

随着以数据驱动为标志的智能时代到来，大数据、云计算、人工智能已与人们的生活和工作紧密联系在了一起。NAND闪存正在逐渐成为支撑智能时代的主要的数据存储器件，但随着其制程尺寸的进一步缩减、多比特/单元存储技术的引入，如何有效提高存储可靠性成为当前面临的一个主要挑战。.本项目从信号处理和差错控制编码的角度出发，对高密度NAND闪存信道干扰噪声和存储可靠性进行了系统深入的研究，具体研究成果包括：1）搭建了闪存信道分析测试平台，基于该平台，研究分析了各类干扰噪声的特性，优化了闪存信道模型；2）提出了一种参考电压实时估计及优化算法、一种后验信息辅助的干扰消除技术和一种基于单元状态的非均匀检测技术，大大改善了信道检测的性能；3）结合闪存信道似然比分布特性，提出了非均匀量化算法；利用闪存单元错误特征关联关系，改进了译码算法；提出了两种消息调度策略，加快了译码算法收敛速度；4）针对数据存储信道设计了一类逼近容量限的码率兼容原模图码，并完善了其性能分析理论。.在该项目的支持下，本课题组发表期刊论文16篇，其中SCI期刊论文14篇，EI会议论文6篇；申请发明专利7件；培养硕士研究生9人，引进培养青年教师2人。