铁电场效应晶体管的负电容效应研究

In recent years, with the rapid development of microelectronics technology, the increasing power dissipation density at the chip level caused by the relentless scaling down of transistors will become a serious challenge for the stability and reliability of integrated circuit (IC). Therefore, finding new ways to reduce the operation voltage and subthreshold swing of the transistor will show very important theoretical significance and application value in the process of reducing power dissipation of chip. Ferroelectric field-effect transistor (FeFET), as one type of ferroelectric random access memory (FeRAM), is currently regarded as one of the most potential next generation memory with clear advantages such as its simple structure, nondestructive read-out operation, irradiation hardness, and compatible with the process of IC. In this project, we will make use of ferroelectric thin film negative capacitance to reduce the subthreshold swing of the transistor. Much attention will be paid to the ferroelectric negative capacitance about its physical mechanism and its influence factors. Proper theoretical model of FeFET will be established to understand the regulating role of ferroelectric thin film negative capacitance effect in the process of switching and storage. Device structure and process parameters of FeFETs will also be simulated and optimized. Finally, it is expected that low operation voltage and low power dissipation ferroelectric field effect transistor for switching and storage uses would be obtained, thus providing some useful theoretical basis and experimental operation instructions for the application of FeFETs in microelectronics logic and storage devices.

近年来，随着微电子技术的飞速发展，集成电路元器件晶体管尺寸不断缩小，芯片集成度不断提高，给芯片带来了日益严重的功耗问题，集成电路稳定性与可靠性面临严重的挑战。因此，寻找新的方法降低晶体管的操作电压和亚阈值摆幅，在解决芯片功耗问题中具有重要的理论意义和应用价值。由铁电场效应晶体管构成存储单元的铁电存储器，由于具有结构简单、非破坏性读出、抗辐照以及与集成电路工艺兼容等优点，而被公认为下一代最具潜力的存储器之一。本项目将利用铁电薄膜负电容能有效应降低晶体管的亚阈值摆幅这一特点，研究铁电薄膜负电容形成的物理机制及其影响因素，建立适当的铁电场效应晶体管理论模型，理解铁电薄膜负电容效应在晶体管开关与存储过程中的调控作用，模拟器件结构和工艺参数并进行优化设计，获得低操作电压、低功耗的铁电场效应晶体管，为铁电场效应晶体管在微电子逻辑与存储器件中的低电压、低功耗应用提供理论依据和实验指导。

近年来，集成电路元器件晶体管尺寸不断缩小，芯片集成度不断提高，给芯片带来了日益严重的功耗问题，集成电路稳定性与可靠性面临严重的挑战。因此，寻找新的方法降低晶体管的操作电压和亚阈值摆幅，在解决芯片功耗问题中具有重要的理论意义和应用价值。由铁电场效应晶体管构成存储单元的铁电存储器，由于具有结构简单、非破坏性读出、抗辐照以及与集成电路工艺兼容等优点，而被公认为下一代最具潜力的存储器之一。本申请项目针对铁电薄膜场效应晶体管的负电容效应开展系统的理论及实验研究工作，获得了一些重要的研究结果。首先，我们基于硅衬底掺杂浓度和温度对铁电负电容的影响，发展了一个硅表面势和漏电流模型，该模型能同时适用于研究硅衬底掺杂浓度和温度对铁电负电容的影响。其次，以PbZr1-xTixO3(PZT)铁电薄膜为栅介质，HfO2为绝缘层，Si为半导体，我们构建了一个MFIS-FET器件模型，分析了PZT铁电薄膜负电容的形成条件，发现锆钛组分比对铁电薄膜的负电容有显著影响，并且在x=0.035附近负电容效应最强，器件表现出最好的性能。通过计算发现，锆钛组分比值x从0.035增加到0.065时，双栅场效应晶体管的亚阈值摆幅从58 mV/dec增加到70 mV/dec，该研究结果能够很好地指导PZT铁电薄膜及场效应晶体管负电容的优化设计。此外，课题组制备了基于金属-铁电-金属结构的二维材料负电容场效应晶体管(2DNC-FET)，利用P(VDF-TrFE)的负电容效应调控二维半导体材料，如MoS2和MoSe2，制备出高性能负电容场效应器件。当源漏偏压为0.1 V时，单层MoS2下的2D NC-FET的亚阈值摆幅为24.2 mV/dec，并且跨越了4个数量级。同时，我们还系统地研究了器件性能随着P(VDF-TrFE)厚度的减小变化的规律。结果发现，器件的亚阈值摆幅随着P(VDF-TrFE)厚度的减小而变大器件性能不断衰减。该研究工作为下一代低功耗电子器件提供了一种新的途径。