粒子检测用混合型阵列探测器可重构像素化读出集成电路研制方法

This project focuses on the design methodologies of radiation-hardened pixel readout ASICs for the upgrade of particle detectors in next-generation high-energy physics (HEP) experiments apparatus. The region-of-interest readout scheme of using reconfigurable hardware to realize the data from the pixel array is proposed for the sake of the enhancement of energy resolution and trigger rate. Thus, it is necessary for the particle-detection applications. This project proposes a detail study in the circuit architecture and new design methodologies of the reconfigurable pixel readout ASIC in nanoscale CMOS technology. The researchers will explore several key scientific issues such as the equivalent-noise charge (ENC) model of the pixel-level charge-to-digital converter (CDC), dynamic reconfigurable strategies of the pixel array data, mixed-mode simulation methods of radiation effects. This project will make a breakthrough on the key techniques including design and measurement of reconfigurable pixel readout ASICs. Such techniques will be the basis of the construction hybrid pixel array detectors for HEP. Moreover, this project will propose the microsystem architecture of reconfigurable pixel readout circuits, design techniques of the CDC, the implemented ways of peripheral readout circuits, radiation-hardened by design methodologies, verification methods via simulations and measurements by the ways of theory research, simulated computing and experimental analysis. The target specifications for the prototype ASIC include the trigger rate of larger than 1 MHz, the ENC of less than 200 e- (rms), the power dissipation of less than 100 μW/pixel，the total dose of 100 Mrad(Si). The proposed design techniques are the basis of the future development of hybrid pixel array detectors for particle tracking.

针对下一代高能物理实验粒子检测系统升级的需求，开展混合阵列探测器抗辐射像素化读出集成电路研究，提出采用可重构电路实现像素级读出电路的控制和对感兴趣数据有选择地读出，能够提高能量分辨率和触发计数率，在粒子检测应用中非常必要。项目拟对纳米CMOS可重构像素化读出电路架构和研制新方法进行深入研究，探索电荷-数字转换等效噪声电荷模型、阵列数据动态可重构策略和辐射效应混合仿真策略等关键科学问题，突破可重构像素化读出芯片设计和测试关键技术，通过理论研究、仿真计算和实验验证相结合，将提出可重构像素化读出电路微体系结构、电荷-数字转换电路设计方法、可重构外围读出电路实现方法、抗辐射加固设计方法、仿真验证和测试评估方法等，使像素化读出芯片的触发计数率高于1MHz、等效噪声电荷小于200e-、静态功耗小于100μW/像素、抗总剂量能力高于100Mrad(Si)，为未来粒子检测用混合型像素探测器研制奠定基础。

本项目开展了应用于高能物理实验粒子探测的混合型阵列探测器像素型读出集成电路设计方法的研究，主要创新工作总结如下：提出了带自动反馈复位的高计数率前端读出电路结构，提高了模拟前端电路的计数率；提出了像素级电荷-数字转换电路架构，实现了光子计数型像素电路阵列；发明了内置LDO超像素电路结构，改善了大阵列像素电路电荷测量的一致性；建立了像素级模拟前端电路的等效输入噪声电荷数学模型，通过低噪声设计和优化，使时域ENC小于80e-(rms)；提出了阵列数据可重构读出方法，实现了并入串出、零抑制和事件驱动等数据读出方法的可重构，减小了稀疏事件读出时间，提升了芯片的系统带宽；揭示了像素型读出ASIC辐射诱发总剂量和单粒子效应机理，提出了相应的辐射加固设计策略，使像素型读出ASIC的抗辐射能力大幅提升；探索了前端读出ASIC的硬件安全体系结构，实现了IP保护电路，为未来像素型读出ASIC的IP保护提供了新思路。基于以上技术，设计了3款像素型读出ASIC原理样片，并进行了性能评估，验证了所提出新技术的有效性。已发表学术论文12篇，申请国家技术发明专利4项。项目执行期间，共参加国内外会议15次，实现了广泛合作交流。在未来，我们将紧扣前端电子学的发展方向，结合高能物理实验、医学成像以及空间射线探测等应用进行全定制大阵列像素型读出芯片的研制。