铁电晶体管存算可调机制和工艺研究

Computing beyond-Moore's Law era requires logic devices with steep subthreshold swings and non-volatile memory devices with high-density. The concept of Negative Capacitance Field Effective Transistor (NCFET) and that of Ferroelectric Field Effective Transistor (FeFET) are promising logic and memory candidates, respectively. They have similar structure but different operation principal. On the basis of our previous study, however, we found that the experimentally observed negative capacitance effect is quite different from the initially proposed concept, and that the steep SS in such a structure is associated with the polarization switching at the coercive voltage on Fe film. This operation is more analogous to FeFET in our view. This indicates the possibility of bidirectional regulation of the logic and storage function in the FeFET under a unified mechanism, and the possibility of fabricating the dual-purpose integrated device. Therefore, this project intends to study the synergistic regulation mechanism of the sub-threshold swing steepness and hysteresis properties of FeFET, to determine the optimal process control of its key materials and device structures, and to realize a dual-purpose ferroelectric logic and memory device. The development of this project will provide a new research roadmap for the integration of energy-efficient computing and non-volatile memory chips in the beyond-Moore era, bring a new perspective to the integration of logic and memory function into one device, and guide the development of other ferroelectric devices.

后摩尔定律时代的集成电路技术亟需具有陡峭亚阈值摆幅的逻辑器件和具有高密度非易失性的存储器件，结构类似但机制不同的负电容晶体管和铁电晶体管概念分别展示了这两个方向的显著优势。然而，申请团队在前期研究中发现该结构中陡峭亚阈值摆幅的实际实现与负电容概念有所不同，而与决定传统铁电晶体管工作的铁电极化反转密切相关。该发现引出了新的科学问题：能否以及如何在统一机制下对铁电晶体管逻辑功能和存储功能进行双向调控，并且据此探索存算一体化铁电器件？该问题的回答具有重要的科学和应用价值。因此本项目拟深入系统研究铁电晶体管逻辑和存储功能的双向调控机制；并对其关键材料和结构进行实际调控；以此为基础，实现统一调控机制下铁电逻辑和存储晶体管器件以及存算一体铁电晶体管器件。本项目的开展将进一步完善铁电纳米电子学的相关理论，为后摩尔时代高能效计算和非易失存储芯片的融合提供崭新的思路，也为存算一体化技术带来新的视角。

后摩尔定律时代的集成电路技术亟需新型高性能低功耗逻辑和存储器件以及存算一体电路架构，结构类似但机制不同的负电容晶体管和铁电晶体管概念分别展示了新型逻辑和存储器件以及在存算一体方面的显著优势。然而，其关联机制和存算一体单元还需要进一步探索，针对这一问题，本项目系统研究了铁电晶体管亚阈值摆幅滞回以及大小的控制机制，在此基础上建立了铁电晶体管逻辑和存储功能双向调控机制；同时对最具应用前景的铪基铁电材料进行调控研究，对其极化强度、极化翻转速度以及耐久性进行协同优化；在此基础上进一步实现了铁电晶体管器件，并通过参数调控实现了陡峭亚阈值摆幅小滞回铁电逻辑晶体管器件以及陡峭亚阈值摆幅大滞回铁电存储晶体管器件。本项目的完成拓展了铁电晶体管器件的基础理论知识，并为存算一体器件和电路单元提出新的途径。