基于InP-Si异构集成的高速高精度数模转换器关键技术研究

High speed and high resolution digital to analog converter (DAC) is the key component in 5G communication, radar and other systems. The purpose of this project is to perfectly integrate the advantages of InP HBT for ultra high speed, high breakdown voltage and Si CMOS for low power consumption and high integration, and to carry out the design of mixed mode circuits based on InP-Si heterogeneous integration. During the project, through theoretical analysis and electromagnetic simulation, vertical heterogeneous interconnection structure will be optimized, and simulation method for coordinated design of heterogeneous transistors will be set up.Through the two methods of changing the type of DAC input code and time-interleaved double sampling, the output spectrum will be expanded. High frequency signal can be directly synthesised with relatively low clock frequency. The proposed transmission line equivalent joint simulation design method will be used to analyze and solve the problems of signal integrity of ultra high-speed mixed signal circuit, improving design flexibility. Simulation speed and iteration cycle will be greatly enhanced. A 14 bit 5GSps DAC chip will be designed. The single ended full scale output analog signal is larger than 1V, SFDR is larger than 50/70dB (broadband / narrowband), DNL/INL is less than±1LSB, and the power consumption is less than 2W. At the same time, the system for testing and evaluating DACs' performance will be set up. The project will lay the foundation for China's heterogeneous integration of high performance mixed signal circuits.

高速高精度数模转换器在5G通信，雷达等系统中都是核心元器件。本项目旨在将InP HBT超高速、高击穿和Si CMOS低功耗、高集成度的优势完美融合，开展基于InP-Si异构集成的数模混合电路设计。项目研究中，通过理论分析和电磁场仿真，优化垂直异构互联结构，建立异类晶体管协调设计仿真方法；通过改变DAC输入码型和时间交织双采样两种方法扩展输出频谱，以相对较低的时钟频率实现高频段信号的直接合成；采用传输线等效联合仿真设计方法，分析和解决超高速混合信号电路的信号完整性问题，提高设计灵活度且在仿真速度和迭代周期等方面比现在方法大大提升。设计14位5GSps DAC样片，模拟信号满量程单端输出摆幅大于1V，SFDR大于50/70dB（宽带/窄带），DNL/INL都小于±1LSB，功耗小于2W。同时搭建DAC芯片性能参数测试和评估系统。为我国异构集成高性能数模混合电路奠定基础。

超高速高精度数模转换器在通信、雷达、导航、卫星、测控、电子对抗和仪器仪表等军用和民用系统中是核心元器件。本项目将InP HBT超高速、高击穿和Si CMOS低功耗、高集成度的优势交叉融合，开展了基于InP-Si异构集成的数模混合电路设计。项目实施中初步完成了异构集成工艺电磁热仿真环境建立；研制出基于InP-Si异构集成的高速高精度数模转换器和单比特数字接收机芯片样片并搭建了测试系统；在Si CMOS，InP HBT和SiGe BiCMOS等单一工艺下研制了超高速直接数字频率综合器，全加器和模数，数模转换器等典型数模混合集成电路芯片；提出了面向数模混合集成电路的传输线等效信号完整性设计和仿真方法，大大缩短了仿真时间和迭代次数。通过本项目的实施，可以在后摩尔时代，在我国完全自主可控成熟工艺上通过异构集成的方法，通过发挥不同工艺性能的优点而避开其缺点，提供了实现高性能数模混合的一种方法，具有非常重要的应用前景。