基于三维载流子注入理论的新型功率SOI-LIGBT器件结构与模型研究

SOI-LIGBT device is the core component of the monolithic power integrated circuit. Improving the current capability without sacrificing the breakdown voltage and reliability is the pursuit goal in design. In this project, base on the theory of three-dimensional carrier injection, innovation research on the foundations and technologies of the SOI-LIGBT is done, including: 1. a novel 600V-class SOI-LIGBT device structure is proposed. By introducing the “three-dimensionalchannel”, the equivalent emitter junction area is increased and the current density is improved. According to the potential sustaining principle of “pinch-off depletion in JFET region”, the surface electrical field in the emitter region is reduced and high breakdown voltage is assured. By using the “high doped p-type buried layer”, the base resistance of the parasitic bipolar transistor is reduced and the immunity capability of latch-up is improved. Finally, the current density of the proposed SOI-LIGBT is improved by about 90% compared with the conventional structure; 2. the analytical model of the current density for the proposed device structure is proposed. According to the model, the optimal relationship between the current density, breakdown voltage and structure parameters is achieved for designing. The structure optimal design is done under the guidance of the model and three- dimension simulation. Finally, an experimental sample of the proposed SOI-LIGBT is fabricated. .This study is an advanced research with the international level. This project has great theoretical significance and practical value.

功率SOI-LIGBT器件是单片功率集成芯片中的核心组件，其关键是在保证击穿电压、可靠性等性能的基础上，实现大电流能力。本项目将基于三维载流子注入理论，对SOI-LIGBT器件基础理论和技术进行创新研究，包括：1. 创新提出一种600V等级SOI-LIGBT器件结构，通过引入“三维沟道”增大器件等效发射结面积来获得大电流密度。通过利用“大器件等区域夹断耗尽”原理降低发射极表面电场强度来保证高击穿电压。通过采用“高浓度P型埋层”降低器件内部寄生三极管基区电阻来实现高抗闩锁能力。最终，器件电流能力相比于传统器件提升90%以上；2. 提出新器件结构电流密度解析模型，获得电流密度、击穿电压和结构参数的优化关系，指导器件设计。利用模型指导与三维仿真对器件进行优化设计，并完成实验研制。本研究系与国际水平同步的超前性研究，意义重大且具有实用价值。

单片智能功率芯片是一种功能与结构高度集成化的高低压兼容芯片，其内部集成了高压功率器件、高低压转换电路及低压逻辑控制电路等。目前，被广泛应用于智能家电、新能源交通工具及智能机器人等高端领域，成为以上系统的核心元件之一。厚膜绝缘体上硅（Silicon On Insulator，SOI）工艺具有寄生参数小、隔离性能好及便于实现高低压集成等优点，成为单片智能功率芯片的首选工艺。在单片智能功率芯片中，基于厚膜SOI的高压横向绝缘栅双极晶体管（Lateral Insulated Gate Bipolar Transistor，LIGBT）被用作开关器件，是该芯片中的核心器件。本项目基于三维载流子注入理论，对SOI-LIGBT器件基础理论和技术进行创新研究。项目执行过程中，已发表相关SCI论文18篇，申请中国发明15项，本项目的主要研究结论如下：.1. 提出了一种提升电流能力的U型沟道技术，该技术增大了注入到漂移区中的电子电流，且电子电流主要在硅表面流动，避免了多沟道技术的缺点。实验结果表明，采用U型沟道技术，SOI-LIGBT器件的电流密度提升了177%，同时闩锁电压达到了500V，击穿电压与比导通电阻的折中关系处于国际领先水平。.2. 建立了新型U型沟道SOI-LIGBT器件电流密度解析模型，模型精确预测了最佳的U型沟道夹角度数。.3. 研究了SOI-LIGBT器件在多跑道并联使用时的非一致关断行为，指出关断失效的根源是边界隔离沟槽所引起的非一致耗尽行为；通过在各跑道之间设置隔离沟槽，解决了器件关断失效的难题，改进后的SOI-LIGBT器件可在450V、饱和电流下正常关断。.4. 提出了一种双沟槽栅极U型沟道SOI-LIGBT器件，在短路电流密度为590A/cm2时，器件的短路承受时间提高了49%。.5. 研究了高压互连线导致器件击穿电压下降的机理，提出了一种双沟槽高压互连线屏蔽技术。该技术采用双沟槽进行耐压，避免了在硅表面形成电场集中。实验结果表明，该技术可100%屏蔽高压互连线对击穿电压的影响，同时高压互连线下方的硅区域长度缩短了66.7%，有效节省了芯片面积。