单片三维相变存储器高速高可靠读取技术研究

Phase change random access memory (PCRAM) is the most manufacturability-promising emerging nonvolatile memory technology. 3D PCRAM, which further combines with monolithic 3D integration technology, has the advantages of high density, high speed, low power, good scalability, etc. It is expected to replace traditional charge-based memory and change the memory-storage hierarchy. However, non-ideal factors like parasitic effects and leakage currents limit the chip’s sensing speed and reliability; the process variations result in the contradiction between speed and reliability; the influence of bias scheme on dynamic performance is neglected. This project intends to study the high speed and high reliability sensing technology of monolithic 3D PCRAM. We will develop the chip dynamic performance analysis method which combines circuits and bias schemes, reveal the influences and principles of the non-ideal factors in circuits and bias schemes on sensing speed, read reliability and their contradiction, and clarify the key non-ideal factors in circuits and bias schemes. We will develop the bias scheme and circuit design technology to suppress the key non-ideal factors and alleviate the contradiction between speed and reliability. We will also develop the bias scheme with low read current and high read margin, and the sensing circuit with an early sensing distinguishing point and low read errors. Finally, we will verify the circuit and bias scheme’s sensing speed and read reliability performance in chip level. This project will promote the development of high-speed and high-reliability 3D PCRAM from basic research to application by solving the key scientific problems behind the bottleneck of sensing speed and reliability and proposing the corresponding design methods and circuits.

相变存储是极具量产潜力的新型存储技术。三维相变存储器，结合单片三维集成技术，具有高密度、高速、低功耗、良好微缩性等优点，有望替代传统电荷型存储器，革新现有存储架构。但寄生、漏电等非理想因素限制了芯片的读取速度和可靠性，工艺波动造成速度和可靠性矛盾，偏置方法对动态性能的影响被忽视。围绕三维相变存储器高速高可靠读取技术，本项目拟发展结合偏置方法和电路的芯片动态性能分析方法，揭示偏置方法和电路中的非理想因素对读取速度、可靠性及其矛盾的影响和原理，阐明偏置方法和电路中的关键非理想因素；发展抑制关键非理想因素、缓解速度和可靠性矛盾的偏置及电路设计方法，研制低读电流、高读裕度的偏置方法和早读取分辨点、低误读取的读出电路；在芯片级验证电路和偏置方法的高速高可靠读取性能；通过解决读取速度和可靠性瓶颈背后的核心科学问题，提出针对问题答案的设计方法和电路，促使高速高可靠三维相变存储器从基础研究走向应用。

三维相变存储器（3-D PCM）是目前最先进的独立式新型存储技术之一。但寄生、漏电等非理想因素限制了芯片的读取速度和可靠性，工艺波动造成速度和可靠性矛盾，偏置方法对动态性能的影响被忽视。本项目对三维相变存储器高速高可靠读取技术进行了研究，取得的主要研究成果如下：.1）提出考虑动态读取性能影响的新型偏置方法。构建了3-D PCM电路级模型，提出的电路级模型包括必要的电路、阵列、偏置方法和器件参数，可以作为工具研究偏置方法对动态性能的影响。发现主要负面影响因素是位线上半选通单元待命和读取阶段的高电压差。在国际上首次提出考虑动态存储性能影响的新型2V/3偏置方法，将电压差从V/2缩小至V/3；使64Mb 3-D PCM读取速度提升29%，功耗下降81%，读裕度上升37%，完全消除误读取，抑制了工艺波动的负面影响。.2）提出一种3-D PCM超高速读出电路，通过采用电压锁存型灵敏放大器，再配合预充电、位线、字线、传输门寄生漏电等匹配技术，实现了约1ns的读取时间，速度比传统技术提高了40倍以上。.3）设计了40nm 3-D PCM读验证芯片，准备流片。包括：设计了一种双向阈值选通器件等效电路；设计了考虑存储单元寄生电容、互连线寄生电阻和电容的1S1R存储阵列；提出了多种选通方案操作步骤，设计了带预充电的快速操作选通方案电路；完成了传统读取电路、新型读取电路、偏置电路、逻辑控制电路、时钟电路、配置电路等外围电路的设计和仿真验证。通过芯片仿真和流片测试等手段验证了电路和偏置方法的高速高可靠读取性能。.本项目面向对国家安全和国民经济有重要意义的存储器领域，取得的成果，为偏置方法对非易失存储器动态性能的影响带来全新的思考，解释了读取速度和可靠性受限的根本原因，突破了芯片低读取速度和可靠性的瓶颈，有助于促使高速高可靠三维相变存储器从基础研究走向应用。.发表标注受本项目资助的SCI/EI论文8篇；其中以第一/通讯作者在IEEE Solid-State Circuits Lett.、IEEE Trans. on VLSI Syst.、IEEE Trans. Circuits Syst. II Exp. Briefs、ISCAS发表论文各一篇。申请发明专利9项。已培养毕业硕士研究生1名。各项技术指标达到验收要求。