动态局部重构密码芯片抗物理攻击关键技术研究

The dynamic and partial reconfigurable crypto chips are widely explored because of the good balance between flexibility and energy efficiency (i.e. throughput/power). However, a key security problem, i.e. how to fully utilize the hardware architecture and computing form of reconfigurable chips to resist against physical attacks, has not yet been solved. This project aims to design efficient physical attack countermeasures for reconfigurable crypto chips in order to improve the overall hardware security. In the project, rich contents, such as the randomness-driven reconfiguration against physical attacks, will be analyzed. A series of key problems, such as the security evaluation and overhead control of time and spatial randomization countermeasures, the physical unclonable function based on reconfigurable cell array, the configuration context encryption and side-channel attack countermeasures, the overall security evaluation method for reconfigurable architecture against physical attacks, will be explored. Besides theoretical analysis and mathematical derivation, the technologies in this project will be evaluated in silicon, FPGA and RTL level as required. The research results of the project will also reserve core technologies of security chip design for our country.

动态局部重构密码芯片因为能够兼顾加解密应用在灵活性与能量效率（即性能功耗比）上的双重需求，在学术界和产业界得到了广泛的研究。然而，这些研究尚未解决如何有效利用此类芯片特殊的硬件架构和计算形式来提升其抵御物理攻击能力的问题。本课题以设计出高效的动态局部重构密码芯片抵御物理攻击的方法和机制，切实提升其硬件安全性为目标，通过研究“随机性驱动的局部及动态重构抗物理攻击技术”等内容，突破“重构引导下时间与空间随机化措施的安全评估与开销控制”、“基于可重构阵列的物理不可克隆函数技术”、“配置加密及其抗侧信道攻击技术”和“重构架构抗物理攻击能力一体化评估方法”等基础科学难题，为大幅增强此类芯片的安全性提供一系列核心技术。除理论分析与数学推导外，本课题会根据需要对这些技术分别进行硅验证、FPGA验证和RTL仿真验证。本课题的研究成果同时也会为我国信息安全芯片的设计进行战略技术储备。

动态局部可重构密码芯片兼具高能量效率和高灵活性，是高性能安全芯片的重要发展方向。本项目突破了“基于时间与空间随机化的重构抗物理攻击技术”、“基于可重构阵列的物理不可克隆函数技术”、“配置加密及其抗侧信道攻击技术”和“重构架构抗物理攻击能力评估方法”等关键技术, 为动态局部重构密码芯片抗物理攻击设计提供了技术支撑。项目研究过程中，发表学术论文15篇，出版著作1部，申请发明专利6项（美国专利2项），2项专利实现成果转化。