片上集成的全数字高速真随机数发生器模型、电路及实现研究

A True Random Number Generator (TRNG) is one of the fundamental parts in a cryptographic system. The performance of cryptographic processor is significantly increased as the CMOS technology advances into the nanometer regime, which, in turn, requires the integrated TRNG also has all-digital and high-speed features...Among four entropy extraction mechanisms most commonly used, the metastability based scheme is the most promising one to meet the requirements, but with three challenges as follows. (1) The metastability-based TRNGs lack a physical model by far that can not only evaluate the stochastic behavior, but also guide the circuit design. (2) The metastability phenomenon is very sensitive to non-idealities and furthermore malicious attack, leading to bias and eventually failure of randomness. (3) Despite all-digital feature, the metastability-based TRNGs are still designed in the full-custom flow, and the automatic design flow fully compatible with the semi-custom flow for VLSI design is not established...The three challenges aforementioned are regarded as TRNG design methodology in this project, and investigated hierarchically. (1) The stochastic differential equation (SDE) is utilized to model the metastability-based TRNG in time domain. The resulted physical model is expected to evaluate TRNG in theory, and optimize the circuit parameters according to the randomness specifications. (2) Calibration techniques will be explored to effectively counteract the circuit imperfection and attacks. (3) Regarding design flow, we firstly categorize the bistable circuitry used in metastability-based TRNGs into comparator type and DFF type, in that they are suitable for full-custom and semi-custom design flows, respectively. Then, the latter will be focused on, and the semi-custom design flow for the DFF type will be built...The accomplishment of this project will pave the way for the self-reliant development of domestic information security chips.

真随机数发生器（TRNG）是密码处理器的核心部件之一；在纳米尺度CMOS工艺下设计的高性能密码处理器迫切要求与之集成的TRNG具备全数字和高速的特点。最具潜力的解决方案是亚稳态TRNG，但它目前还在物理模型、电路结构和设计流程三个方面面临许多挑战。本项目将其统一为TRNG的设计方法展开研究，重点解决以下关键问题。首先，提出基于随机微分方程，从时域建立亚稳态TRNG的物理模型，这样既可以从理论上说明随机原理，也可以优化电路参数；其次，根据亚稳态的条件，在电路结构方面探索有效的反馈校准方法，既能抵消非理想因素，又能抵御人为攻击；第三，提出将亚稳态核心结构分为比较器型和触发器型两类，根据两者不同的特点分别用全定制和半定制的设计流程实现，希望最终建立兼容于VLSI设计的自动化设计流程。本项目的完成将提高TRNG的设计效率与成功率，为自主研发国产高性能信息安全芯片奠定基础。

真随机数发生器是信息安全领域的核心器件，对其自主可控更是国防信息安全的迫切需求。本项目对片上集成真随机数发生器的理论模型、电路设计和测试方法进行全面的研究。首先，在理论方面，将比较器亚稳态随机微分方程模型应用于亚稳态熵量化器，得到了电路参数与数据率的定量关系，以此作为熵量化器设计中电路参数选择的理论指导。其次，在测试方法上，利用平均熵速率随着采样频率的提高而饱和的现象，提出了一种最大熵速率的测试方法，为真随机数发生器提供了一种新的动态测试方法。第三，在电路设计方面，为了易于与处理器片上集成，采用可编程延时链反馈架构：一方面在FPGA平台上利用查找表方式实现一款全数字真随机数发生器，并验证电路架构的正确性；另一方面在芯片平台，我们提出了一系列真随机数发生器的电路设计技术，解决了芯片设计中有限的硬件资源与高鲁棒性需求之间的矛盾，在此基础上实现了一款高鲁棒性的全数字真随机数芯片设计，测试结果表明其数据率不低于1.7Gbps，单位能耗不高于6pJ/bit，等效输入失调电压范围最大可达200mV，并易于通过数字流程实现。本项目取得的成果将对国家的信息安全领域作出贡献。