基于忆阻器交叉阵列实现存内处理技术的功耗与可靠性关键问题研究

The applications with deep learning are featured of high parallelism, simple computations, data intensive and poor data locality. Consequently, the problems of “Memory Wall” and reliability are getting severer with the conventional Von Neumann architecture. Addressing the problems, RRAM crossbar-based Processing-In-Memory (RPIM) has been proposed to provide solutions because it can avoid quite a few data movements between computation part and memory part. The previous studies mainly focus on techniques for performance improvements, but with few discussions targeting power and reliability issues. In this project, we have the following insightful observations by investigations on power and reliability issues of RPIM. First, the power consumption of peripheral circuits part of the RPIM system is significantly high to become the tough bottleneck. Second, the power consumption of RPIM system can often exceed power budget which is originally planned for the function of only data access but with no consideration on parallel computing. Third, process variations during manufacturing can lead to reliability problems and degrade application accuracy. The last, IR-drop and sneak-path can bring variations to computations and also lead to accuracy problem. Addressing all these problems, this proposal will come up with a series of solutions following the idea of software and hardware codesign such as task scheduling with a specifically designed architecture, resistive value redefining and delayed pipeline scheduling combined with DVFS, weights remapping and compensation, weight matrix blocking, etc. With these efforts, it is expected to reach the project goal of eliminating or mitigating the power and variation problems of RPIM system. This study can initiate extensive research on power and reliability issues of RPIM system, and further boost its solid real-world applications.

在当今深度学习算法的应用背景下，传统的冯·诺依曼结构已经不能适应计算并行度高、数据密集和局部性差等应用特征，导致“存储墙”和功耗问题日益严峻。基于忆阻器交叉阵列的存内处理技术是当前学术界和工业界正在积极探索的有效途径之一。过去在该方向上的研究以提升存内处理部件的性能为重点，对功耗和可靠性方面的研究不够充分。本项目针对存内运算部件中外围电路功耗高的瓶颈问题、高度并行计算导致的存内运算部件功耗超预算问题以及器件工艺变动、电压降和潜通路等偏差导致的可靠性问题，以跨越电路、体系结构和软件等多层次的思路提出软硬件协同优化的技术路线（如结合电路复用结构的层调度技术、配合DVFS的阻值重定义和流水线延时调度技术、权值调整和权值网络分块技术等），最终达到消除或缓解上述功耗及可靠性问题。本项目的研究成果可为基于忆阻器交叉列的存内处理技术的深入发展提供关键技术，为其应用推广提供有力的技术支撑。

深度学习、数据挖掘等算法应用背景具有计算并行度高、数据量相对较大、数据局部性不显著等特征，在传统冯·诺依曼架构下计算系统的“存储墙”和“功耗墙”问题日益严峻。基于忆阻器交叉阵列的存内处理技术是学术界和工业界当前正在积极探索的有效解决途径之一。过去在该方向上的研究以提升存内处理部件的性能为重点，对功耗受限的场景特征以及系统可靠性方面的研究不够充分。. 本项目着眼于存内运算部件中的功耗瓶颈和以及交叉阵列中由电压降现象引发的算法精度和系统可靠性等关键问题，从跨越电路、体系结构和软件等多层次的思路提出软硬件协同优化的技术路线，针对物联网、边缘智能计算等应用背景开展了能效优化和可靠性加固方案探索。主要研究内容包括两个方面：（1）能效优化：探讨了边缘计算场景下应对供能功率受限条件下的低功耗、可重构存内处理加速器架构设计以及与之协同的卷积计算任务的弹性分配和调度策略，构建相应的加速器软硬件协同设计思路和方案。（2）可靠性加固：探讨了忆阻器交叉阵列中电压降、潜通路及加速器计算精度的定性关系，构建了阵列单元的阻值偏差分布的量化分析模型，分别从硬件层次和软件层次提出了偏差补偿方案来加固系统可靠性。. 本项目的研究成果以期为存算一体技术加速器的深入应用提供关键设计思想和技术支撑，推动体系结构、集成电路和设计自动化相关领域的技术研究和产业发展。