高k介质/拓扑绝缘体界面结构的物理和电学特性研究

With the discovery of the high mobility carriers in the topological insulator surface, a new type of high performance materials for the next generation of integrated circuits comes into the view of the device community. However, from the current status of research on topological insulator based transistors, the excellent transport properties at the surface of topological insulator severely degraded when it is integrated into electronic devices. This target of this project is to obtain the high-quality high-k dielectrics/ topological insulator interface and its corresponding physical and structural model, the high mobility topological insulator based prototype devices as well as the corresponding device model. Through the optimization of precursors used in atomic layer deposition, high-k materials, topological insulator materials and the fabrication processes, the project will achieve low damage or damageless topological insulator/high-k dielectrics interface structure. Based on the research above, the crystal structure and the electronic structure of the topological insulator/high-k dielectrics interface, the impact mechanism of the high-k dielectrics to the carrier mobility at the surface of topological insulator will be investigated in detail. Through theoretical modeling, testing of the micro-structure at the interface and characterizations of the device, the electrical parameters of the high-speed low-power device with high-quality high-k dielectrics/topological insulator interface and the device model will be both extracted. Finally, the integration of optimized processes and characterization methods, a topological insulator based prototype electronic devices with the mobility exceeding 1000 cm2/Vs will be obtained in this project.

拓扑绝缘体表面高迁移率载流子的发现，为用于未来更高性能的集成电路的场效应晶体管提供了新型高性能沟道材料。然而，从国内外的研究来看，拓扑绝缘体本身优异的输运性能并未能在电子器件中得到体现。在本项目中，将以获得高质量的高k介质/拓扑绝缘体界面体系及其相关的物理和结构模型，高迁移率的拓扑绝缘体原型器件及其模型为目标。通过原子层淀积前驱体、高k材料、拓扑绝缘体材料的甄选和工艺优化，获得低损或无损的拓扑绝缘体/高k介质界面结构。 在此基础上，研究该拓扑绝缘体/高k介质界面的晶体结构和电子结构，高k介质对表面载流子迁移的作用机制，获得该界面的载流子传输机制和界面能带特征。通过理论建模，微结构测试和器件测试三方面的综合分析，研究以该界面为基础的高速低功耗拓扑绝缘体原型器件的电学特性，并提取器件模型。 最后，整合各项优化的材料与工艺，实现迁移率超过1000 cm2/Vs基于拓扑绝缘体的原型电子器件。

随着Si也逐渐接近其物理极限时，二维半导体（主要为TMD）及拓扑绝缘体（TI）被认为是下一代集成电路中有望延续摩尔定律的重要材料，引起了科学界的广泛关注。但TMD或TI材料表面没有悬挂键，致使原子层淀积高k介质难以在TMD/TI表面均匀成膜。.针对以上问题，本项目从高k材料制备工艺的开发，薄膜性能的优化以及器件性能的表征等方面开展了一系列的研究工作。根据课题组研究计划，本项目主要开展了基于原子层沉积技术的TMD/TI材料上的开发及其器件应用技术，重点完成了基于原子层沉积的n型MoS2材料开发、p型WS2材料开发，同时针对获得的材料，开展了器件集成技术研究。.本项目主要结合原子层沉积技术以及新型的TMD和TI材料，开展了新型电子器件的研究。主要完成了如下研究目标：.（1）利用原子层沉积技术结合氮原子预掺杂技术，突破了原子晶体p/n掺杂调控的难题，实现了p/n可控的晶圆级TMD材料（如MoS2和WS2）的生长；.（2）完成了新材料的器件集成，其电子迁移率和空穴迁移率分别达到25.5 cm2/Vs和18.8 cm2/Vs，开关比超过1E4。.此项技术打破传统制备工艺难以大面积集成的缺陷，开阔了TMDs材料大面积合成及稳定掺杂的研究思路。.项目发表受标注论文11篇，其中SCI论文10篇。