3D堆叠众核处理器共享存储访问均衡性研究

With the rapid development of integrated circuit technology, System-on-Chips (SoCs) are evolving from bus-based single core/multi-core architectures to network and DSM-based many-core architectures using 3D stack technology, named 3D stacked many-core processors, thus becoming the efficient way of supporting on-chip high-performance parallel computing. In 3D stacked many-core processors, the partitioning and organization of level 2 distributed and shared memories, parallel memory access conflicts in target memory controllers, and the delay difference of parallel memory access requests routing in 3D NoC make the equalization problem of shared memory access be more serious, which becomes the heavy bottleneck of the system performance. Therefore, we plan to carry out deep research on the equalization of shared memory accesses in 3D stacked many-core processors, break through the key technologies of shared memory access in 3D stacked many-core processors, and gain some innovative results. The main work includes: 1) memory access equalization oriented level 2 distributed shared memory organization technique; 2) parallel memories grouping and parallel requests scheduling technique that supports equalized responses; 3) DRAM requests scheduling technique supporting equalized responses; and 4) fair flow control technique based on variable priority and the prediction of total routing delay. Finally, we will construct the simulation platform and the FPGA emulation environment of the 3D stacked many-core processor that contains more than 128 cores and supports shared memory access equalization.

随着集成电路技术的快速发展，片上系统逐渐由基于总线的单核或少量多核结构发展到基于片上网络和分布式共享存储的大量多核（众核）结构，并采用3D堆叠技术，该结构称为3D堆叠众核处理器，是支撑片上高性能并行计算的有效途径。在3D堆叠众核处理器中，二级分布式共享存储的划分和组织方式、并行访存请求竞争、3D片上网络延时差异等使得共享存储访问的均衡性问题日趋严重，成为系统性能瓶颈。本项目拟针对3D堆叠众核处理器的共享存储访问均衡性问题展开深入研究，突破3D堆叠众核处理器访存关键技术，取得原创性研究成果。主要研究内容包括：1）面向访存均衡性的二级分布式共享存储划分技术；2）支持均衡响应的并行存储编组和并发访存调度技术；3）支持均衡响应的DRAM访存请求调度技术；4）基于可变优先级和总路由时长预测的均衡流控技术。最后，将建立具有共享存储访问均衡性的128核以上的3D堆叠众核处理器模拟平台和FPGA仿真环境。

随着集成电路技术的快速发展，片上系统逐渐由基于总线的单核或少量多核结构发展到基于片上网络和分布式共享存储的大量多核（众核）结构，并采用3D堆叠技术，该结构称为3D堆叠众核处理器，是支撑片上高性能并行计算的有效途径。在3D堆叠众核处理器中，二级分布式共享存储的划分和组织方式、并行访存请求竞争、3D片上网络延时差异等使得共享存储访问的均衡性问题日趋严重，成为系统性能瓶颈。本项目针对3D堆叠众核处理器的共享存储访问均衡性问题展开了深入研究，取得了原创性研究成果。主要研究内容是：1）面向访存均衡性的二级分布式共享存储划分技术、2）支持均衡响应的并行存储编组和并发访存调度技术、3）支持均衡响应的DRAM访存请求调度技术和4）基于可变优先级和总路由时长预测的均衡流控技术。在研究论文的实验中，构建了具有共享存储访问均衡性的128核以上的3D堆叠众核处理器模拟平台和FPGA仿真环境。本项目在国内外重要刊物和国际会议上发表高水平学术论文9篇，其中SCI检索5篇，EI检索4篇，包括ACM Transactions on Embedded Computing Systems顶级期刊和IEEE Transactions on Very Large Scale Integration (VLSI) Systems顶级期刊，申请国家发明专利4项，培养硕士生2名，协助培养博士生3名。本项目的研究工作对提高片内数据的服务质量，缩短各核访存延时差异，从而提高3D堆叠众核处理器整体性能具有重要意义。相关研究成果可广泛应用于高性能并行计算领域。