基于电荷等离子体的不掺杂隧穿场效应晶体管的物理机理与解析模型研究

Tunnel field-effect transistor (TFET) attracts extensive interests for its subthreshold swing can break through the fundamental thermionic limitation of MOS devices, hence enabling the reduction of supply voltage, which is especially suitable for low-power applications. Conventional TFET suffers from the requirement of highly-doped Source-Channel abrupt junction, which is a difficult problem for the TFET fabrication. Dopingless tunnel field-effect transistor (DL TFET) makes Source/Drain electrically “doped” based on the Charge-Plasma concept instead of conventional physically Source/Drain doping, thus no highly-doped abrupt junction is needed in DL TFET while maintaining the advantages of steep subthreshold swing. This project plans to investigate this novel device and build the analytical model. Based on solving Poisson’s equation with boundary conditions with the consideration of the mechanism of the electrically “doping”, the physics-based potential distribution model will be built. WKB integral will be calculated from the potential model and E-k relations, and then the analytical model for tunneling current will be built. The physical insights of subthreshold swing degeneration will be carefully analyzed, and the key factor that describes how severe the SCE is in DL TFET and the scaling theory will be proposed. The project’s objective is to thoroughly depict the physical insights of DL TFET based on the analytical model, and provide some theoretical basis in the aspects of helping choose novel device among candidates for low-power VLSI and guiding the device design.

隧穿场效应晶体管（TFET）因其亚阈值摆幅可突破MOS器件的理论极限值，可用于较小的工作电压，尤其适合低功耗应用，而引起广泛关注。传统TFET需要高掺杂的源-沟道突变结是其工艺制造上的一个难题。不掺杂隧穿场效应晶体管（DL TFET）基于电荷等离子体概念对没有物理掺杂的源、漏进行电学“掺杂”，不需要高掺杂突变结的同时，具有亚阈值摆幅较小的优点。本项目拟针对该器件开展解析模型研究，通过构建反映电学“掺杂”机理的泊松方程和边界条件框架，建立基于物理本质的DL TFET电势模型；结合电势分布和材料E-k关系计算WKB积分得到隧穿几率，进而建立隧穿电流解析模型；分析亚阈值摆幅退化机制，提出描述DL TFET中短沟效应严重程度的关键参量和缩比理论。以期基于解析模型，反映DL TFET器件的物理本质，为低功耗应用集成电路在新型元器件选择和指导器件优化设计等方面，提供一定的理论基础。

新型不掺杂隧穿场效应晶体管（DL TFET）基于电荷等离子体概念对源、漏进行电学“掺杂”，可解决传统TFET工艺制造上需要高掺杂源-沟道突变结的难题，同时具有亚阈值摆幅可突破MOS器件理论值的优点。本项目针对该器件开展物理机制和解析模型研究。通过数值仿真和理论分析刻画了DL TFET的物理特性和工作机理，建立了DL TFET中源、漏电学“掺杂”解析模型；建立了双栅TFET和DL TFET的能带/电势模型和隧穿电流模型，并通过TCAD仿真进行模型验证；建立了适用于隧穿器件的电荷和电容模型；研究了短沟效应对DL TFET亚阈值摆幅的影响。在此基础上，提出了一种新型电荷等离子体线隧穿场效应晶体管 (CP LTFET)，在不掺杂场效应晶体管中实现了线隧穿。该器件通过引入电荷等离子体源/漏和非对称双栅结构，在不掺杂晶体管中实现了电学掺杂和大的线隧穿面积，从而可以获得较高的开态电流。结果表明，建立的TFET和DL TFET解析模型与TCAD数值仿真结果吻合良好。提出的新型CP LTFET实现了高开态电流、低关态电流、陡峭的亚阈值摆幅SS。并且相较于经典DL TFET，CP LTFET的性能对源极金属功函数、栅极金属和源极金属之间的间距以及栅极绝缘层厚度的变化等参数相对不敏感，进一步降低了隧穿器件的工艺要求。在本项目的支持下，发表了SCI/EI收录论文6篇，申请中国发明专利5项，其中3项已获得授权。