面向大规模图计算的FPGA加速器关键技术研究

As the scale of Big Data analysis applications grows dramatically, the large scale graph processing plays a more and more important role in Big Data era. Graph processing has been challenging the traditional general central processing processors due to its features including load imbalance, irregular memory access, low compute memory access ratio and lack of locality. Recently，the FPGAs-based accelerator has been attracting more and more attention from both industrial and academic institutions. FPGAs has been a more promising computing platform against central processing processors in terms of fitting applications, high parallelism and high energy efficiency...This project presents a high performance graph processing accelerator according to the research and development trends of graph processing. In order to alleviate the challenges of FPGA-based graph processing in aspects of customized hardware data structure, locality of data, performance analysis model and graph processing framework, several studies are proposed. Firstly, we propose the optimized hardware parallel algorithms and customized hardware data structure for typical graph processing problems. Secondly, we introduce a software-hardware co-design method to enhance the locality of data. Thirdly, a refined performance analysis technique based on the performance loss metrics is present. Finally, we develop an FPGA-based graph processing framework with flexibility and sustainable optimization ability. This project will provide several key techniques to increase the performance and energy efficiency for the next generation of high energy-efficient Big Data analysis computers.

随着大数据分析应用数据规模的不断增长，大规模图计算在大数据分析应用中的作用日益凸显。图计算具有负载不均衡、访存不规则、计算访存比低、局部性差的特点，给传统的通用微处理器带来严峻挑战。相对于通用微处理器，以FPGA为代表的加速器在拟合应用特点、并行性和高能效方面具有较大优势和应用前景，越来越引起工业和学术界的重视。.课题结合FPGA图计算加速器的研究和发展趋势，面向FPGA图计算面临的硬件数据结构、数据局部性、性能分析模型和图计算框架等方面的挑战，研究面向典型图计算问题的的FPGA定制计算硬件结构、软硬件协同的数据局部性增强机制、基于性能损失度量的精细化性能模型分析技术和灵活好用可持续优化的图计算处理框架等关键技术，为下一代面向大数据分析的高效能计算机提供有力的计算和存储方面的技术支持。

本项目以提升大规模图计算应用的性能为目标，重点从处理器/FPGA加速器的角度探索面向图计算的加速器设计技术。通过探索在自主处理器核心中增加数据载入流水线、访存子系统参数对访存延迟影响评估、融合发射队列设计等方法，为进一步提升了自主处理器的通用计算性能给出了技术支撑，为下一步设计高性能图计算处理器打下了研究基础。SPEC2006的测试结果表明，在当前基础处理器中增加一条取数据流水线可以提高程序运行性能高达10.90%，平均为2.75%。针对BFS算法的测试实验结果表明，在基础处理器中添加一个额外的取数据流水线和一个算术逻辑计算部件对自顶向下、自底向上和混合BFS算法可以分别实现 8.5%，2.7%和 2.4%的性能提升。这些研究成果目前已经应用到当前自主处理器当中，未来将结合实际芯片效果进一步进行确认和测试，以验证研究成果应用的有效性。