体系结构/算法级嵌入式GPU低功耗策略的研究

In the age of Post-PC, the Embedded GPUs (EGPU) with the powerful computing performance and flexible programmability have gained wide attention because of the urgent requirements for gorgeous visual experiences. But the excessive power dissipation has restricted EGPUs development. This proposal will analyze the power characteristics of EGPU. And according to the problems causing the power dissipation such as excessive pressure of memory bandwidth requirement, low datapath utilization and existing mass of useless graphic data, it will systematically carry out the research of low power design in EGPU at the both architecture and algorithm levels through the whole graphic pipeline. The main study contents includes EGPU low power memory hierarchy fusing the texture and vertex accessing characteristics, low power unified shader based on datapath utilization improvement and useless graphic data rejection based low power fixed-function graphic pipeline and hardware architectures. The above research results will be evaluated on the EGPU full system HW/SW co-simulation platform so as to verify them playing a very significant role in reducing EGPU power and improving the power efficiency. The research of this proposal will contribute to break the "Power Wall" when EGPU is applied in the mobile devices. And it also will provide the support at the level of architecture and algorithm for promoting the deploying of graphic applications with gorgeous visual experiences in the mobiles.

后PC 时代，用户对绚丽视觉体验的迫切需求使具有强大计算性能和灵活可编程性的嵌入式GPU (EGPU)备受关注，但过高的功耗始终是制约其发展的瓶颈。本课题剖析EGPU功耗特性，针对存储带宽需求压力大、数据通路利用率低以及存在大量无用图形数据等造成其功耗损失的难题，贯穿EGPU整条图形管线，系统地从体系结构和算法两个级别寻求EGPU低功耗设计的突破，主要研究内容包括：融合纹理/顶点访存特性的EGPU低功耗存储体系、基于改善数据通路利用率的低功耗统一着色器以及基于无用图形数据剔除的低功耗固定管线算法和硬件结构，并利用本课题开发的EGPU全系统软硬件协同仿真平台对上述研究成果进行评估，证明其在降低EGPU计算和访存功耗，提高功耗效率上具有显著的作用。该项研究将有助于打破EGPU应用于移动设备时所遭遇的“功耗墙”，为具有更逼真视觉体验的图形应用能够在移动终端上得以部署提供体系结构和算法上的支持。

本课题针对嵌入式GPU对存储带宽需求压力大、数据通路利用率低以及存在大量无用图形数据等造成其功耗损失的难题，贯穿EGPU整条图形管线，系统地从体系结构和算法两个级别寻求嵌入式GPU低功耗设计的突破。首先，为了缓解多着色器嵌入式GPU的顶点处理压力，本课题提出缓存SRAM数据与tag索引分离的松耦合Post-顶点Cache结构，缓解顶点传输压力。接着，本课题设计了一种能同时支持细粒度和粗粒度cache line管理的L1 data Cache，可针对不同图形应用的访存特点改变cache line的大小，以适应不同的访存模式。再者，本课题提出一种线程-通道混洗压缩策略，大幅改善了嵌入式GPU着色器的数据通路利用率。最后，本课题提出一种基于掩码屏蔽平面的EZT 算法和相应的硬件架构，实现了对于嵌入式GPU固定管线中的无需处理片元的最大化剔除。基于上述优化体系结构和算法，本课题将嵌入式GPU的平均性能提升15.3%，平均功耗降低21.8%，有效改善了嵌入式GPU的能效。