面向低功耗数字电路应用的多晶锗硅纳机电开关研究

Due to zero leakage current and unlimited subthreshold slope, nano　electro-mechanical relay(NEMS relay) is the ideal candidate of device constructing nanometer low power digital circuit. Nowadays NEMS relay can't be integrated with digital integrate circuit smoothly because there still exists a great gap between fabrication process，electrical parameters and reliability of NEMS Relay and the reqirement of digital integrate circuit. Research of poly SiGe NEMS Relay oriented to low power digital circuits application is proposed in this project: nanometer gap is realized by last beam process combined with optimal lateral device structure, consequently actuate voltage of NEMS Relay can be reduce to fit the requirement of nanometer digtal circuits. The scheme of metal covering on sidewall can reduce on resistance of the device, meanwhile misplace of gate electrode and beam intentionally can avoid adhesion effectively thus the reliability of the NEMS Relay is improved. Based on the FEA method the mechanical and electrical characteristics of the NEMS Relay are estimated and device parameters are optimized, accordingly macro device model of the NEMS Relay is built, combined with circuit simulation tools the efficiency of NEMS Relay of reducing power consumption of circuits is evaluated. LPCVD technique is utilized to fabricate low stress high quality poly SiGe film, furthermore low temperature poly SiGe NEMS relay fabrication process is investigated and the proposed poly SiGe NEMS Relay is manufactured. The research achievements will lay the foundation of device, model and fabrication process of the NEMS Relay oriented to low power digital circuits application, and additionally provide new avenues of research of breaking through the power bottlenecks of nanometer integrated circuit.

纳机电开关具有零漏电流、超低次临界斜率的特性，是构建纳米尺度低功耗数字集成电路理想的替代和补充器件。但目前纳机电开关在工艺兼容性、电学参数及可靠性上，距离纳米尺度数字电路的需求还存在较大差距。本项目拟开展面向低功耗数字电路应用的多晶锗硅横向纳机电开关相关研究：采用后梁工艺结合优化的横向结构实现驱动电极与梁间的小尺寸间距，以降低启动电压；利用侧壁金属层方案减小导通电阻，同时通过驱动电极与悬臂梁错位的方法避免粘附，以提高器件可靠性；基于有限元分析评估器件性能，优化器件结构参数，并建立电路仿真宏模型，利用宏模型评估该器件所构造电路的性能；采用多层工艺，利用低压化学气相淀积技术，制备低应力多晶锗硅薄膜，探索与CMOS兼容的多晶锗硅纳机电开关低温制造工艺，研制和测试多晶锗硅纳机电开关。研究结果将为面向低功耗数字电路应用的纳机电开关奠定器件、模型及工艺基础，为突破纳米尺度集成电路的功耗瓶颈提供新途径。

纳机电开关具有低能耗、尺寸小等优势，是构建纳米尺度低功耗数字集成电路理想的替代和补充器件。本项目重点针对其在器件结构、制备工艺及性能等方面与现有硅基CMOS器件/工艺的兼容性问题进行研究，主要研究工作包括：新型纳机电开关器件结构模型的构造和优化，并系统研究了各工艺环节对纳机电开关器件性能的影响，及气隙间距、电机尺寸、介质厚度的合理设计及优化；采用后梁工艺突破机电开关间隙间距无法缩小到纳米尺度的限制，解决了纳机电开关启动电压偏大的问题。开发了纳机电开关器件的一系列关键工艺，诸如多层介质各向异性刻蚀工艺、纳米尺度牺牲层气相释放工艺、电极表面CMP工艺等，最终实现了上述工艺的集成和器件制备，完成了纳机电开关器件的电学测试。结果表明：与传统MEMS器件相比，本项目的纳机电开关在器件性能及工艺兼容性方面具有优势。同时，针对当前新兴的石墨烯材料，项目开展了对石墨烯微纳机电系统的前期研究，完善了石墨烯界面无损无残留的转移工艺，提出了一种使用纳米压痕仪对多层石墨烯测量的方法，通过多场耦合的方法得到石墨烯纳机电开关的静态位移特性和固有振动特性；并初步开展了石墨烯纳米机电结构的工艺探索。为未来对于纳机电开关的研究进一步拓宽思路。