CPU/GPGPU紧耦合异构多核系统共享Last Level Cache优化研究

Integrated technology of core on chip is fast developing, greatly promoted Heterogeneous multicores on-chip system。In these systems, various resources are shared between CPUs and GPGPUs,the last-level cache（LLC）is one of the most important shared resources that affects the overall system performance especially the on-chip communication and Resource utilization. The project targets a tightly fused multi-core on-chip system of CPU and GPGPU, analyzing the different memory model from the Heterogeneous cores,figure out the optimization method of last-level cache. In detail，this project's research points are as follows: under the GPU and CPU tightly - coupled multiprocessor architecture, we analyze the effects imposed by using shared last-level cache architecture on Computing model, and classify the factors that affect the last-level cache performance,then build up a memory performance model; According to the differences memory reference patterns among of cores on the GPU and CPU tightly-coupled Heterogeneous system, there need be some Mechanisms to manage the last-level cache, typically,dynamic partitioning, reconfigure which including set cache inclusive or exclusive and replace LRU, Data Migration, better cache coherence protocol and data filtering; improve memory reference efficiency to shared last-level cache and efficiency of Task scheduling, reorder memory references from cores on Heterogeneous multicores system，improve the way that thread mapped to Heterogeneous multicores system, dynamiclly reconfigure task mapping according to last-level caches' performance，study the factors the last-level cache imposed on threads' Priority of CPU and GPU; build up the performance evaluation model of shared last-level cache, verify the impact shared last-level cache on computing model.

随着片上核心集成技术的发展，极大地推动了异构多核片上系统的发展，它们通常具有共享LLC，从而使整个系统的通讯和资源使用更加高效。本项目面向CPU+GPGPU的紧耦合异构多核片上系统，根据异构的核心对共享LLC访存模式的差异以及LLC上数据的相互共享和干扰，研究优化LLC的方法。具体内容包括：分析CPU+GPGPU紧耦合异构多核系统下共享LLC的架构对计算模型的影响，建立LLC访存性能模型；针对CPU+GPGPU紧耦合异构多核系统共享LLC数据访问模式，设计共享LLC动态划分，重配置LLC的组织结构，调整插入替换策略等，实现数据迁移，改进一致性以及提供数据过滤方法; 共享LLC访存与任务调度优化，对异构核上的访存进行重排，优化线程在异构核上的映射方式，运行时重配置任务的映射，探索LLC对CPU和GPU线程优先级的影响因素；共享LLC性能评估模型的建立，验证共享LLC对计算模型的影响。

片上核心集成技术的发展极大地推动了异构多核片上系统的发展，它们通常具有共享LLC，从而使整个系统的通讯和资源使用更加高效。.本项目面向CPU+GPGPU 的紧耦合异构多核片上系统，根据异构的核心对共享LLC 访存模式的差异以及LLC 上数据的相互共享和干扰，研究优化LLC 的方法。本项目研究了GPGPU的访存行为模式，提出了GPGPU上的等距离访存融合，实验得到了51%的性能提升。进一步探索了CPU+GPGPU紧耦合异构多核系统上共享LLC 的数据访问模式，提出了紧耦合异构架构的模拟器，总结了CPU和GPGPU并行运行时的访存行为特点，发现LLC主要改善GPGPU的性能，而对CPU的性能提升较小，但若不优化访存调度，CPU会被GPGPU访存严重影响。数据过滤方面，研究了访存调度改进与共享LLC旁路，实验表明在不同测试集上分别提高了6.01%和3.52% 的性能。线程和访存调度方面，提出了同步感知的GPGPU warp调度算法和同步感知的访存调度算法，同时应用两个方法可获得0.02%到21.47%的性能提升。在共享LLC计算模型方面，研究了CPU和GPGPU数据交换优化，提出了两种共享LLC数据交换缓存，平均性能提升分别为60.5%和48.2%。.本项目共发表了学术论文31篇，其中期刊论文10篇、会议论文21篇，申请专利5个（4个已授权），培养研究生8名。