基于高Q值射频阻抗合成器的自适应抗阻塞射频接收系统理论及电路研究

The popularity of the Internet of Things (IOT) makes the number of wireless communication terminals working in the same frequency band increase rapidly. Various wireless terminals in the environment greatly increases the probability of blocking. The adjacent blockers have worse effects on the reception of the signal than the blockers which are far away from the useful signal at the frequency. Conventional RF receiving system structure implements SAW filters, which increase the cost, to filter out the blockers. But in-band blocker cannot be effectively suppressed. Therefore, SAW-less blocker-tolerant RF front-end system has become the focus of recent academic research. This project proposes an adaptive blocker-tolerant RF receiving system theory based on high-Q RF impedance synthesizer. to improve system frequency selectivity，higher order impedances will be constructed and an innovative system architecture is proposed; Spectrum shift theory based on passive mixer will be discussed and non-ideal factors will be analyzed and applied to guide circuit design; Detecting blocking strength, changing impedance synthesizer capacitance resistor network by digital baseband circuit, adaptive frequency selectivity can be achieved; Designing verification circuits and taping out to verify the correctness and superiority of the theory proposed in this project. The research results of this project will provide theoretical guidance for high frequency selective blocker-tolerant RF receiving system and circuit design.

物联网的普及使得工作在同一频段的无线通讯终端数目迅速增多，环境中众多的无线终端大大增加了信号阻塞的产生几率。相比在频率上与有用信号间距较远的阻塞信号，邻近的阻塞信号对信号的接收过程影响更大。传统射频接收系统结构通过外加声表面波滤波器（SAW）的方式来滤除阻塞信号，这种方法增加了成本而且对接收频段内阻塞信号无法进行有效抑制。因此无声表面滤波器（SAW-less）抗阻塞射频接收系统得到了业界关注。本项目提出一种基于高Q值射频阻抗合成器的自适应的射频接收系统理论。通过构造高阶阻抗和改进系统架构提升系统频率选择性；深入研究基于无源混频频谱搬移理论，分析其非理想因素，并以此指导电路设计；检测阻塞强度，并通过数字基带电路选通阻抗合成器电容电阻网络实现自适应的选频特性；设计验证电路并制作样片，验证本项目提出的理论的正确性与优越性。本项目研究成果将为高频率选择性抗阻塞射频接收系统及电路设计提供理论指导。

随着物联网的发展，工作在同一频段的无线通信终端数目迅速增多，众多同时工作的无线终端增加了信号被阻塞的产生几率。传统接收机通过外接表面声波滤波器（Surface Acoustic Wave，SAW）的方式滤除带外阻塞，但是这种方案限制了系统集成度的提高，且不能有效滤除通信频段内相邻信道上的阻塞，因此全集成抗阻塞接收机得到业内的广泛关注。. 为了提高系统邻近阻塞抑制比，本项目提出一种基于高Q值射滤波器抗阻塞射频接收系统设计方法，在系统架构、电路理论和关键电路模块方面开展了深入的研究。在系统架构上，提出了一种基于高Q值滤波支路抗阻塞射频接收系统架构。该架构通过在射频放大器输出端和中频电路中间级，逐级滤除阻塞信号。通过数字基带电路检测当前阻塞信号的功率强度，选通合适性能的低噪声放大器，避免阻塞在滤波之前使电路饱和。在电路理论上，利用伴随网络数学方法，建立了一种简化的无源混频器模型，明确了各电学参数对混频器影响；在关键电路模块上，提出了一种高阻带抑制比和高Q值射频带通滤波器，该结构基于无源混频器的频谱搬移特性，将跨阻级的中频输入阻抗特性搬移到射频本振处，并采用负阻提高了滤波器Q值；研究了无源混频器输入级与输出级负载电容之间存在的电荷共享效应，提出利用电荷共享效应，构造复数阻抗，提升射频滤波器邻近信道阻塞抑制比；当阻塞强度不足以使常规低噪声饱和时，本项目提出一种非平衡噪声抵消高能效低噪声放大器；当阻塞强度较高时，本项目提出一种基于电感负反馈高线性度低噪声放大器，容忍阻塞。. 基于28nm工艺设计了验证芯片，测试结果表明基于电荷共享滤波器的抗阻塞前端在低功耗应用中具有较强竞争力，其带外线性度达到了-0.35dBm、噪声系数为6.8dB、功耗仅为0.4mW，信号频偏20MHz处的阻塞抑制比达到50dB，在由无杂散动态范围和功耗定义的优值上达到世界一流水平。