异构多核嵌入式实时系统能量高效与故障恢复关键技术研究

Energy efficiency and fault recovery are the essential foundations to ensure the embedded system to work persistently and reliably. These two promote each other, whereas restrict each other. Through the research approach of hardware and software co-design, the heterogeneous multi-core embedded hardware platform is constructed, and the energy-efficient scheduling and control-flow error recovery mechanism of the multi-core real-time system are studied. By doing this, both the energy cost and the run-time reliability of the real-time embedded system can be optimized. As the application of the embedded system is diverse, a heterogeneous multi-core hardware architecture supporting dynamic voltage and frequency scaling (DVFS) is proposed. By scaling the performance of different cores dynamically, a hardware platform adapted to the software features can be constructed. By researching the time and energy multi-objective optimization scheduling algorithm, the energy cost of the embedded system can be optimized while the service time of the real-time tasks can also be guaranteed. Aiming at the problems that the energy cost of the fault-tolerant system is high and the fault detection program is easy to fail, the heterogeneous multi-core architecture which separates the fault detection program from the main program in the hardware design is constructed. Aiming at the challenges of control-flow concurrency in the heterogeneous multi-core system, the multi-core control-flow model based on the colored Petri net theory is built. By combining this model with the label-based control-flow fault detection algorithm, the system control-flow errors occurred during the run-time can be recovered. Expected results will optimize the energy cost and improve the fault recovery ability, will enhance the performance of the embedded device and promote the development of the embedded technology.

能量高效与故障恢复是嵌入式系统持久可靠工作的两大基础，两者相互促进，互相制约。通过软硬件贯通的研究方法，构建异构多核嵌入式硬件平台，研究多核实时节能调度算法与控制流故障恢复策略，实现嵌入式实时系统能耗与可靠性综合优化目标。针对嵌入式应用多样化特性，提出支持动态电压调整的异构多核硬件构架。通过动态调整各处理核性能，构建出匹配软件特性的硬件平台。研究异构多核系统能耗与时间多目标优化调度算法，在满足服务时间前提下，最大程度优化能耗。针对故障检测系统能耗高且检测程序易失效问题，提出检测程序与主程序硬件分离的硬件构架。针对异构多核系统程序控制流高并发、异步等特性，研究基于有色Petri网理论的异构系统控制流规约模型。结合此规约模型与标签分析控制流检测算法，实现对异构多核系统控制流故障的检测。预期成果将延长设备工作寿命，修复系统控制流故障，将增强嵌入式系统持久可靠工作性能，促进嵌入式技术发展与应用。

当前，在智能计算领域，研究工作较多地关注智能计算算法的精度优化，而对算法的计算时间以及能耗的优化则较少考虑。然而，在许多实际智能计算应用中，需分析的数据量巨大或数据生成的速度极快，且这些数据需要以实时、低能耗成本的方式进行智能处理。在这些应用场景中，算法的计算时间与能耗具有和算法精度同样重要的优化研究价值。算法的精度优化可以仅从软件算法层展开研究，而算法的计算时间与能耗优化则需从算法底层的系统层与硬件层进行协同优化。.本课题采用软硬件系统贯通的研究方法，构建一种基于异构计算的AIoT（AIoT = AI + IoT，人工智能物联网）赋能的端、边、云协同的智能计算系统平台，实现对大数据智能计算应用的算法精度、计算时间以及计算能耗的综合优化。.（1）在硬件层，针对算法高密集计算部分，设计一种专用的FPGA硬件加速器，通过硬件直接实现算法，提高算法的计算速度与能效。.（2）为增强计算硬件对不同软件上下文的自适应能力，将FPGA加速器与CPU、GPU处理器组合，构建出“通用+专用”架构的CPU/GPU/FPGA异构计算节点，实现硬件结构特性与软件算法特性的高度匹配。.（3）针对所构建的异构计算节点，研究一种实时、高能效异构系统任务调度方法，实现任务在不同硬件计算单元间的最佳分配，进一步提升计算系统的计算速度与能效。.（4）为使异构计算系统具备实时处理大规模数据的能力，更进一步地采用Kubernetes等分布式技术，构建出分布式异构计算系统平台。.（5）将上述异构计算平台按照不同配置方式，部署到边缘端与云端，实现边、云协同计算。.（6）研究异构计算节点控制流故障检测与恢复支撑技术，提高异构计算节点的运行可靠性。.本课题重点研究上述智能计算系统架构中的FPGA硬件加速器设计、CPU/GPU/FPGA分布式异构计算平台构建、异构系统高能效实时任务调度算法、异构系统控制流故障检测与恢复等内容。设计了面向MobileNet CNN算法以及FFT数据处理算法的FPGA加速器；构建了真实的CPU/GPU/FPGA分布式异构计算平台；研究了基于Q-learning算法的异构系统调度方法；提出了基于硬件的程序运行故障现场快速卷回恢复技术。.研究成果已应用到了武汉市全时全域智慧地铁系统，以及新建的湖北鄂州民用机场工程智能跑道应用中，在实现大规模数据实时、低功耗、智能化处理方面，发挥了重要作用。