纳米CMOS工艺高速数模混合锁相环频率合成器非理想特性模型研究

This proposed research project will resolve the difficulty of suppressing the non-idealities in the ICs on the basis of nm-CMOS process for ultra-high speed communication system in the theoretic and practical aspect. This research project concentrates on the theoretic derivation and measurement applications of the non-idealities model in digital-analog hybrid PLL-type frequency synthesizer based on the nm-CMOS process. Combining digital radio frequency integrated circuit chip design and measurement technology, novel methods of the verification and optimization will be established for the digital-analog hybrid PLL-type frequency synthesizers with complex structures and operation frequency over 10GHz. The technique methods researched will be adopted in the chip design of Digital RF front-end Chips. The aim of the proposed project is to promote the accuracy of derivation and measurement for the non-idealities of Digital RFICs

本项目的研究将为解决纳米CMOS数字化射频前端电路中的非理想特性瓶颈问题提供有力的理论与技术支持。研究将围绕纳米CMOS工艺高速数模混合型锁相环频率合成器的非理想特性的理论模型理论及其的测量与验证方法开展创新性研究。通过结合数字射频集成电路芯片的设计与测试技术，建立新的工作在10GHz以上频段的复杂结构数模混合锁相环频率合成器非理想特性模型的验证与优化方法，并探索其在数字化射频前端芯片中的应用。目标是为改进数字化射频集成电路的非理想特性模型的测量与验证的准确度提供新途径。

本项目围绕纳米CMOS工艺高速数模混合型锁相环频率合成器的非理想特性的模型理论及其测量与验证方法开展创新性研究。本项目建立了具有较为复杂结构的数模混合锁相环频率合成器非理想特性噪声行为级仿真模型的算法用于分析纳米CMOS工艺高速数模混合型锁相环频率合成器整体的非理想特性噪声；本项目还设计了用于纳米CMOS工艺高速数模混合型锁相环频率合成器非理想特性噪声测试验证系统，完善了非理想特性噪声模型的测试协同技术。在此基础之上，本项目将上述研究成果用于指导相关的CMOS射频芯片的设计，改善了电路的性能。