多通道脑电信号采集模拟前端芯片的超低功耗小型化设计技术研究

Brain-Machine interface (BMI) has been widely used in medical and scientific research areas, which makes ultra low-power and miniaturized implantable or wearable multi-channel EEG recording device very important. However, the analog-front end (AFE) chip is one of the main circuits that can affect the performance of the entire multi-channel EEG acquisition system.. In this program, under the direction of the AFE systematic models, the ADC switching-energy, matching, and noise models proposed by the applicant previously, the modeling research and architecture optimization of the multi-channel EEG recording AFE are performed with respect to the chip area and power dissipation. A novel low-noise amplifier (LNA) structure without input DC-blocking capacitance is proposed to reduce the chip area and a low-power design technique with the combination of energy-efficient switching scheme and signal pre-detection method is proposed for the successive-approximation-register (SAR) ADC to reduce the power consumption of the AFE chip. From the design aspect of the entire system-on-chip (SoC), the complexity of the power management block is dramatically reduced by a small-area full-MOS reference generation circuit combined with a multi-output low-dropout regulator (LDO). For further power reduction, a low-leakage design technique in nano-scale CMOS process is proposed for the multi-channel EEG recording AFE chip. Moreover, to make the AFE chip more applicable in implantable devices, data packeting circuit and internal clock self-generation circuit are designed for reducing the number of input/output (I/O) PADs. Finally, an ultra low-power and small-area 64-channel EEG recording AFE chip are realized in a 65 nm CMOS process. The theoretical research and design techniques in this program are very important for multi-channel AFE design and optimization, which can facilitate the development of BMI systems.

脑-机接口已广泛应用于医疗及科研等领域，其中植入式或穿戴式多通道脑电信号(EEG)采集器件的低功耗小型化设计至关重要，而模拟前端(AFE)芯片是影响整个EEG采集系统性能的关键电路。本项目以申请人前期获得的AFE系统模型、ADC能耗、匹配及噪声模型为指导，针对多通道EEG采集AFE的功耗和面积进行建模研究和结构优化，提出一种无输入电容的小型化LNA电路结构以及结合低功耗电容阵列切换和信号预检测的SAR ADC设计技术以减小AFE功耗和面积。此外，提出完全基于MOS器件的小型化基准电路并采取多输出结构LDO简化电源电路复杂度，提出纳米级CMOS低漏电设计技术进一步减小功耗，并设计数据打包以及内部时钟产生电路以减少芯片的端口数目，提高其应用的灵活性，最后基于65nm CMOS完成64通道EEG采集AFE芯片的超低功耗小型化设计。本项目能够指导多通道AFE设计优化，提高国内脑-机接口设计水平。

高性能模拟前端芯片在工业、国防、生物电子等领域都具有广泛应用，其低功耗小型化电路技术是限制其植入式、穿戴式、便携式应用的关键因素。此外，脑-机接口在生物医疗和生命科学研究方面都具有重要作用，而模拟前端(AFE)芯片是影响整个 EEG 采集系统性能的关键电路。本项目主要研究低功耗小型化模拟前端电路技术、模数转换器的功耗、面积、精度协同设计技术、高效无线数据发射电路技术以及低压低功耗电源管理电路技术。重要结果包括：提出多种适用于逐次逼近ADC的高能效小型化电容阵列及其逻辑控制方式，并在此基础上设计验证了多款低功耗小型化ADC芯片；采用反馈量衰减技术以及T型电容网络设计技术，有效减小了模拟前端LNA电路的面积；提出了用于模拟-时间-数字转换的新型二进制减法电路，并采用非线性校准技术设计实现了一种基于VCO的ADC，面积仅为类似指标逐次逼近ADC的1/5；提出一种具有快速响应的低压差线性稳压器，输出过冲和下冲的电压幅值能够分别下降35.3%和78.1%，响应速度提高了7.41倍；提出一种具有输出幅度增强的无线数据发射电路技术，输出脉冲幅度较传统UWB发射电路提高了2倍；基于CMOS工艺设计实现了多通道脑电信号采集模拟前端芯片，芯片面积和功耗满足预期指标要求。本项目所研究的内容和取得的关键技术能够指导多通道AFE设计优化，提高国内低功耗集成电路设计水平。