面向下一代移动智能设备的CMOS片上全集成低压差稳压器的研究与设计

Low-dropout regulators (LDOs or LDRs) are indispensable components for power management applications in mobile devices, providing well-regulated supply voltages for the noise-sensitive blocks, such as analog, mixed-signal, RF, and certain low-voltage digital circuits in system-on-chip’s (SoCs). Traditionally, one or more off-chip capacitors are used as the output filtering and stabilizing elements for an LDO, such that the regulated voltage has fast responses and low ripples. However, on one hand, the modern SoCs have evolved to be more and more complicated ones, and hence the required amount of supplying LDOs increases dramatically, in order to achieve optimized power profiles for the various functional blocks. On the other hand, not only the system board space will be very limited in the next-generation mobile and wearable devices, but the allocated pin number for power converters will also be quite insufficient. In view of this trend, fully-integrated LDOs that support output-capacitor-free operation are largely demanded, which can save board space, pin number and bill-of-material (BoM) cost at the same time. However, without an off-chip capacitor’s assist, a fully-integrated LDO has slow responses when load current or line voltage changes, leading to large spikes and noises in its output voltage. The supply spikes and noises will seriously degrade the reliability and performance of the functional circuits, and so LDOs that achieve fast load transient responses and high power supply rejections (PSRs) should be developed to alleviate this problem. Existing designs usually have insufficient response speeds, take large quiescent currents, require high dropout voltages, or consume large chip areas. In this research, we propose to study the design of fully-integrated fast-response LDOs. We will explore techniques that enable the LDOs to achieve fast load transient responses and high PSRs over a wide frequency range, while maintaining low quiescent current, low dropout voltage and compact chip area. Moreover, we will perform in-depth theoretical analysis on the fully-integrated LDOs such that comprehensive design guidelines can be provided.

低压差稳压器是移动设备中的关键电源转换器，为片上系统的噪声敏感模块—如模拟、混合信号、射频和部分低压数字电路—提供稳定的电源电压。传统的低压差稳压器需要片外电容以获得快速响应和低纹波，然而片上系统的功能趋于复杂，为优化各模块的供电，需用的稳压器数量急剧增加;而且，下一代移动和可穿戴设备中，系统空间及管脚数量都将非常紧张。因此，无需片外电容的全集成低压差稳压器将有巨大需求。不过，没有片外电容的稳压器其响应速度会受到极大限制，严重影响负载的工作，因此，需要快速响应的低压差稳压器来缓解此问题。现有的设计存在各种缺陷，如响应速度不够、消耗过大的静态电流、需要高压差、芯片面积过大等。在本项目中，我们将探索快速响应的全集成低压差稳压器设计技术，以获得快速瞬态负载响应和宽频带的高电源抑制比，且保持较低静态电流，低的压差以及较小的芯片面积。同时，我们也将对稳压器进行全面的理论分析以给应用提供设计指导。

由于下一代移动设备所用的片上系统芯片功能趋于复杂，所需的给SoC供电的低压差稳压器（LDO）数量越来越大，而系统空间及管脚数量都非常紧张，因此，无需片外电容的全集成LDO有巨大需求。而没有片外电容的协助，低压差稳压器的性能受到极大限制，特别是响应速度、环路带宽等性能难以满足实际需求，功耗和面积指标也难以优化。为解决这些问题，本项目开展CMOS片上全集成、高带宽、快速响应的低压差稳压器的研究与设计。本项目在执行过程中，设计并流片验证了多款性能领先的全集成LDO稳压器，能够针对移动设备的不同应用场景进行优化。其中有代表性的三款LDO稳压器如下：（1）基于动态密勒补偿的全集成、高宽带、快速响应低压差稳压器，采用0.18um标准CMOS工艺流片，所消耗的静态电流仅为8.5uA，压差为0.2V，当负载电流在0.1mA到100mA之间跳变时，输出电压下冲和过冲仅分别为38mV和37mV，恢复时间仅分别为0.4us和1.22us。（2）基于负电荷泵增强的全集成低压差稳压器，采用65nm标准CMOS工艺流片，静态电流21uA，输入电压低至0.6V、且压差仅为0.1V，当负载电流在1mA到45mA之间跳变时，输出电压下冲和过冲仅分别为29mV和65mV，稳态时输出电压纹波不超过1.7mV。（3）基于数字辅助的数模混合式控制全集成稳压器，显著提高负载能力，采用0.18um标准CMOS工艺流片，所消耗的芯片面积仅为0.022平方毫米，压差为0.2V，支持0到150mA范围负载电流，负载调整率为0.17mV/mA。同时，本课题也将研究适度扩展到应用于LDO输入端的参考电压源设计方面。基于本项目已发表了12篇SCI期刊论文、15篇IEEE会议论文，已申请了5项国家发明专利，其中3项已获得授权，并获得1次最佳论文奖；辅助培养了1名博士后、2名研究生，以及多名本科生。以上这些设计以及相关的其他设计的完成，为本领域的科学研究提供了重要参考，也为满足下一代移动智能设备的各个不同模块、不同工作模式的电源供给提供了有实际价值的借鉴。