深度学习算法可重构加速器关键技术研究

Deep Learning algorithms are state-of-art Machine Learning techniques and the most important category of contemporary AI algorithm. The scope of applications and the scale of data using these algorithms are all growing fast. Deep Learning algorithms are computationally intensive due to its processing characteristics of multiple iterations and large scale matrix manipulation, which naturally leads to investigate acceleration technology as a "hot topic" in recent research committee. FPGA is one of the most suitable platforms to implement high-performance Deep Learning algorithms. Previous studies have focused only on customized accelerators of Deep Belief Networks which are lack of flexibility and analysis on accuracy implications. Reconfigurable accelerator architecture for the mainstraem Deep Learning algorithms will be studied in this project. The extraction technology of common procedures and the special operations in those algorithms will be investigated and an uniformed algorithm template will be induced. An analysis model of accuracy will be built to evaluate the effect of fixed-point representation. A kind of asynchronous architecture for Deep Learning algorithms accelerator based on FPGA will be proposed, among which several optimization methods in hardware design will be deeply studied. The design methods of parameterized accelerator circuit and the automatically generation technology of the accelerator will be explored. We finally aim to implement a demonstration FPGA system and a circuit generator for the accelerators of Deep Learning algorithms. The generator can generate an optimized accelerator circuit automatically for a Deep Learning algorithm. The accelerator then can be configured into the demonstration system to achieve high-performance and high accuracy for a specific application. Our tools thus can provide high performance and high applicability at the same time, which can be widely used in many machine-learning tasks.

深度学习算法已成为机器学习领域最新最重要的一类人工智能算法，应用范围和数据规模日益增大。由于涉及多次迭代和大规模矩阵运算，该类算法处理成为典型的计算密集型过程，其加速技术渐成为近年的研究热点。FPGA是实现高性能深度学习算法的有效平台，而目前的研究仅限于对深度信任网络这一种特定算法的定制实现，不能满足该类算法集合中各种改进和变形流程的加速需求，适用性差，算法精度影响分析不足。本项目将针对主流深度学习算法集合，研究算法流程共性和特异性,归纳统一的算法模板，建立定点化精度影响分析模型；面向FPGA特征，提出可重构的深度学习算法异构加速器体系结构，重点研究一套有效的硬件实现和加速优化方法；研究加速器参数化设计方法和自动生成技术，实现一个面向深度学习算法典型应用的可重构FPGA加速器原型系统和一个加速器自动生成软件系统，满足算法精度要求，全面提高这类算法加速应用的性能和灵活性，应用前景广阔。

深度学习算法已成为机器学习领域最新最重要的一类人工智能算法，应用范围和数据规模日益增大。由于涉及多次迭代和大规模矩阵运算，该类算法处理成为典型的计算密集型过程，其加速技术渐成为近年的研究热点。FPGA等低功耗平台正在成为定制化实现深度学习加速引擎的有效平台之一。.利用大规模并行的浮点部件实现深度学习网络模型代价很大，定点运算更适合定制实现大规模并行专用电路，但定点化所带来的精度影响需要深入研究。项目针对多种典型深度学习网络模型提出了深度学习网络定点化评估模型和评测方法，分析了多种深度学习网络定点化表示、运算策略、近似化方法对算法精度影响，给出适应硬件并行的定点化实现结论。.以定点化精度分析为研究支撑，项目提出了针对典型深度卷积网络的FPGA多级并行加速处理结构，开发了CNN网络卷积层和全连接层的多种粒度并行性，在FPGA平台上的实现结果表明，加速器可获得相较于主流通用CPU 10倍以上的性能加速比和相较于主流GPU 10倍的性能功耗比；针对低功耗小型化应用，项目提出了能够处理深度学习算法矩阵运算要素的超向量协处理器结构，DBN和Sparse coding网络在此结构上的实现结果表明，该结构在保证可编程灵活性的同时，可达到相较于主流CPU约9倍的性能功耗比。.为提高加速器的适用性，提出了基于高级硬件描述语言的深度学习网络加速器自动生成器，生成器能根据一定设计约束搜索具有最优执行时间、资源代价和性能等指标的生成电路，典型深度卷积网络模型LeNet、AlexNet、VGG等的生成及测试结果表明，生成器可自动实现高性能的硬件电路，同时大大缩短了设计时间。.项目成果所提供的算法加速器可作为实际智能系统的加速引擎直接使用，适合应用于小型化一体化的智能装备，也可用于构建更高效能的大规模机器学习处理平台。