高精度可变集成模拟延时线的设计方法研究

While the ultra-wideband (UWB) phased-array radar and its associated processing, variable non-dispersive delay line is currently facing challenging topics. The methods of traditional analog delay line and software delay in terms of bandwidth and real time are difficult to meet the UWB radar requirements. In this project, based on true-time delay (TTD) skill and resorting to the idea of delay locked, we presents a high-precision configurable analog delay line method, which is providing a viable approach for solving the technical problem. This project is face up to the requirements of wide frequency-band and wide incidence angles. Based on the two key problems including "high speed" and "high precision", we mainly research optimization delay units, the accurate delay circuit employing delay reference loop and some key skills, such as on-chip passive devices designs, delay configurable skill, the optimization of circuit structures etc. We will build the modeling library of signal delay units, present the configurable schemes employing the accurate delay circuits and eliminate the bottlenecks of contradiction among "high speed", "high precision" and signal delay fidelity. The correctness of the design method on signal delay circuits designed will be demonstrated by designing circuits, analyzing EM field, taping out and test. This project will provide the new means for radar detection scanning to improve the performances, and establish the theoretical and technical foundation of improving the signal delay's application in the complicated EM environments.

超宽带（UWB）时控阵雷达及其相关处理中，非色散可变延时线是目前面临的挑战性课题。传统的模拟延时线和软件延时方法在带宽和实时性方面难以满足UWB雷达的要求。本项目基于实时延时线（TTD）技术，借助延时锁定思想，提出高精度可调节的模拟延时线实现方法，为这一技术难题的解决提供可行的途径。本项目针对宽带宽角的要求，围绕"高速"和"高精度"这两个关键问题，从最优化延时单元和延时参考环精确延时电路研究着手，对片上无源器件，延时可调节，电路结构优化等关键技术进行研究，建立延时单元模型库，提出精确延时电路可配置方案，突破"高速"和"高精度"与信号延时保真的技术瓶颈。通过电路设计、电磁场分析、流片和测试，验证延时电路设计方法的正确性。本项目将为进一步提高超宽带相控阵雷达监测扫描性能提供新的技术手段，为下一代超宽带阵列雷达信号延时精确控制奠定理论和技术基础。

随着无线通信技术的迅速发展，人们对相控阵雷达的性能需求也在不断地提高。近年来，在人们对超宽带(UWB)时控阵雷达的研究当中，非色散可变延迟线是目前面临的挑战性课题。研究的具有宽带、延时分辨率高和延时可调节等特点的模拟实时延迟线电路，为解决这一技术难题提供了一种可行的途径。. 研究了一个宽带短时延有源实时延时单元电路。用差分有源电感和单晶体管构成二阶全通滤波器结构，电感采用跨导倍增和负阻抗技术，实现低的感值和高的谐振频率。用TSMC 0.18μm工艺进行流片验证，测试结果表明：在 3-12 GHz 频带内，该延时单元电路的延时范围为6-8.5ps。. 研究了一个基于延时锁定环结构(DLL)校准的宽带有源延时线电路，以提高电路的抗干扰能力。对DLL结构进行了系统建模和行为级仿真，分析了输出信号的抖动和瞬态锁定时间的影响因素，提高环路的性能。用TSMC 0.18μm工艺进行流片验证，测试结果表明：在0.6~4.2GHz频带内具有5ps的延时分辨率和95ps的延时范围。. 研究了两款数控模拟延时线电路。数控阵列电路采用了路径共享技术，构成一个四通道可编程延时阵列，在0.4~1.3 GHz频带内实现-150~300ps延时，精度为10ps；另一个则采用数字控制单元，在2.5~4.5GHz带宽内实现0~143ps的延时范围，精度为8.5ps。. 研究了一个工作在K波段的无源延时线电路。电路用电容和与金属互连线形成基本延时单元。用IBM 0.13μm SiGe 工艺流片测试，该电路在14~34GHz频带内具有5ps延时分辨率和35ps的相对延时范围。基于以上研究基础，还研究了无源/有源结构结合的延时线电路，进行了流片测试。. 项目致力于宽带模拟延时集成电路的研究，完成了多个宽带实时延迟线电路的设计与实现，为宽带波束成形系统阵列研究提供了技术支撑。