面向5G背景无线接收机应用的模拟集成电路关键技术研究与电路设计

With the progress in CMOS technology, the performance-per-power of digital circuitry increases greatly, and that of RF circuitry improves as well. In comparison, analog circuitry is confronted with more and more challenges. Motivated by the development of mobile communication technologies and by the growth of economic demands, the integration of wireless receiver and application of digital circuitry both increase significantly. However, analog baseband is still a necessary bridge between RF frontend and analog-to-digital converter (ADC); unless battery lifetime and heat dissipation problem are both settled. Besides, Bandgap Reference and Low Dropout (LDO) regulator are also indispensable components for receivers. These analog signal processing modules and bias generators are both implemented with analog circuitry, which is challenged in modern CMOS processes. Meanwhile, these analog blocks are faced with demanding requirements in the Next-Generation mobile communication system. Oriented to the wireless receiver applications, this research proposed to employ linearized transconductance cells, current feedback amplifiers (CFAs) and operational current amplifiers (OCAs) to design analog baseband and LDO regulator, which are key analog blocks in a wireless receiver. In this case, the more and more server trade-off between input offset, closed-loop bandwidth, settling time and power consumption in traditional OTA is avoided. The proposed research approach will be verified by measurement results of chips, and a theory on Very Deep Sub-Micro CMOS analog circuit design will further be set up.

随着CMOS制造工艺的不断进步，数字电路的性能功耗比大幅提升，射频电路的性能功耗比亦有改善，但是模拟电路却面临诸多挑战。移动通信技术的发展和经济需求的增长推动着无线接收机的集成化和数字电路的广泛应用，但是，在电池技术和散热技术无革命性突破的情况下，模拟基带链路依然是射频前端和模拟数字量化器之间必不可少的桥梁。模拟基带链路模块和诸如基准源、低压差稳压器等不可或缺的偏置产生模块，都是由模拟电路实现的，不但受到工艺进步带来的挑战，还面临新一代移动通信提出的更苛刻的性能要求。面向无线接收机对模拟集成电路的需求，本课题提出利用线性化跨导单元、电流反馈放大器和运算电流放大器设计模拟基带链路和低压差稳压器的思路，以规避传统运算跨导放大器在先进工艺下所面临的失调与闭环带宽、建立时间、功耗之间的越来越严重的矛盾。最终以芯片的测试结果验证研究思路，并建立起一套甚深亚微米CMOS工艺下的模拟集成电路设计理论。

随着微电子制造技术和的超大规模集成（Very Large Scale Integration，VLSI）电路规模的不断发展，以及学科交叉的进一步深化，信号处理数字化、射频-模拟-数字电路的集成化日益发展，推动着片上系统（System on Chip，SoC）化快速发展的同时也给模拟电路设计提出诸多挑战，比如电压空间紧张、MOS管本征增益下降、MOS管栅极漏电更加显著等基本问题。封装系统（System in Package，SiP）是目前兼顾大系统集成和高性能模拟电路性能的基本手段，但是难以降低成本且不利于进一步的系统体积小型化。SoC方案仍然是更大规模电子系统小型化的重要途径，并且越来越多的使用先进的纳米级工艺制程。本课题针对模拟集成电路在SoC应用下遇到的挑战，从三个方面开展了理论研究或者系统验证:（1）研究了电流模运算单元的特性与其在CMOS实现时遇到的困难，并且在与广泛使用的电压模运算单元——运算跨导放大器（Operational Transconductance Amplifier，OTA）对比研究的过程中，提出区分负反馈类型的新方法；基于该方法能够更直观的看出为什么电流负反馈不会受到增益-带宽折中的制约。（2）提出高输出阻抗电流源的低压降实现方案，通过建立数学模型进行理论分析，给出了稳定性条件；这种基于正反馈的电流源只需要单层MOS管就可以实现与共源共栅结构相当的输出阻抗，但是噪声性能有所恶化。（3）在电路系统应用中验证上述技术。基于运算电流放大器（Operational Current Amplifier，OCA）设计了一个宽带且恒定带宽的可编程增益放大器（Programmable Gain Amplifier，PGA）以验证电流模单元的实用性；基于所提出的电流源设计了1.1 V电源电压下的高性能OTA，验证了其作为源极耦合对的尾电流源的有效性，因为它的噪声贡献会以共模的形式被后级电路抑制；在常规电源电压下设计宽带高增益OTA的实验也证实了所提出电流源的价值。此外，本课题还深入研究了高性能PGA、中高速度模数转换器（Analog to Digital Converter，ADC）、无片外电容低压差线性稳压源（Low Dropout Linear Regulator，LDR）等模拟模块的设计。