3D堆叠式全并行事件驱动型视觉传感器研究

Owing to its low redundancy, sparsity, fast response characteristics, vision sensors with address-event representation have a good future in the field of high speed imaging, detection, target tracking. However, its pixel size and delay in large array arbitration severely limit its resolution. This project works with 3D stack technology, and build a three-dimensional and parallel vision sensor architecture from the planar design. The vertical parallel signal path makes signal delay much lower. The separation of light sensitive devices and readout circuits allows smaller pixel size and higher resolution. The detailed contents in this research are summarized as follows. Based on the study of the vent triggered vision sensor with 3D stack architecture, a stacked fully parallel vision sensor model and architecture have to be built; Fully parallel real time target detection can be achieved with the study on fully parallel high dynamic range photo-electronics conversion and subtraction type event generation method; With the block parallel fair sequence arbitration, target can be restored completely even in the condition of large amount of events. Based on all these results above, a 512×512 stacked fully parallel event triggered vision sensor design can be accomplished, and key modules such as sub-array, event generation, and fair arbitration, should be verified on silicon. These achievements can provide theoretical and technology resources in the high speed event triggered vision sensors with large pixel array.

地址-事件表示型视觉传感器以其低冗余、超稀疏、高速响应等优势，在超高速成像、检测、目标追踪等领域拥有广阔的应用前景，但其像素尺寸和大阵列的仲裁延迟严重限制了传感器分辨率。本项目结合3D堆叠工艺技术，将平面传感器架构立体化、并行化，提出垂直并行的信号传输架构，缩短延迟，同时感光器件和电路分离，缩小像素尺寸，突破事件驱动型传感器的分辨率限制。具体研究内容为：通过研究3D堆叠结构的事件驱动型异步视觉传感理论，建立多层次全并行的视觉传感器模型和架构；研究全并行高动态光电转换和减除式事件产生方法，实现全并行实时目标探测；研究分块并行的公平次序仲裁读出机制，保证大量事件触发时的完整目标还原。最终完成512×512以上多层次堆叠的全并行事件驱动型视觉传感器设计，并对子阵列、事件产生、公平仲裁等关键模块进行流片验证，为大规模像素阵列的高速异步事件驱动型视觉传感器提供理论指导和技术来源。

地址-事件表示型视觉传感器以其低冗余、超稀疏、高速响应等优势，在超高速成像、检测、目标追踪等领域拥有广阔的应用前景，但其像素尺寸和大阵列的仲裁延迟严重限制了传感器分辨率。本项目结合3D堆叠工艺技术，开展3D堆叠高并行的事件驱动视觉传感器芯片的研究。.本项目针对高速仿生视觉传感器在速度、分辨率提升方面的局限性，在新型3D堆叠工艺技术的指导下，通过3D堆叠层间互连方式的分析，建立了3D堆叠视觉传感芯片的模型和失效分析，基于上述分析提出了3D堆叠成像芯片的高可靠层级化布局方法，进而完成了3D堆叠视觉芯片的模型和架构的搭建。在芯片模型和架构的指导下，项目开展了高性能像素设计方法、事件驱动方式的公平仲裁等异步读出电路设计方法的研究，从而完成了1000×1000像素40Gb/s数据吞吐率高速视觉传感芯片设计和128×128、400×250阵列两款视觉芯片的流片验证。两款验证芯片均可实现0.05ms以下的高响应速度。课题组进一步基于上述3D堆叠设计思想和事件驱动设计方法开展了基于事件驱动、3D堆叠分块并行等方式的信号测量方法、荧光寿命成像等专用测量芯片的扩展研究。.综上，本项目从3D堆叠互连方式、芯片互连架构故障分析、仿生视觉传感芯片模型、像素和电路设计方法以及仿生传感芯片和算法等方面完成了3D堆叠事件驱动的仿生视觉传感芯片的研究，发表高水平论文10篇，其中SCI检索9篇，申请发明专利5项，协助培养研究生6人，形成了3D堆叠的仿生视觉传感理论和芯片、算法的初步技术体系，为大规模像素阵列的高速异步事件驱动型视觉传感器提供理论指导和技术来源。