基于SOI的横向SJ等效耐压层理论及新结构

The concept of the equivalent voltage sustainable layer (EVL) is introduced in the lateral SJ-LDMOS based on SOI. The EVL is defined as the combination of the charge compensation layer and the dielectric layer. The voltage capacity of the lateral SJ is similar to that of the vertical SJ by the innovative research on the model and technology of the lateral SJ. Three innovatives is as following: (1) The EVL model is established and the breakdown mechanism of the lateral SOI SJ device is revealed. The series solution of the surface field and the simplified electric field of N/P middle line are obtained by solving 3D Poisson's equation in the drift region,and the optimal doping is achieved by solving the surface field distribution of the EVL with arbitrary doping charge compensation layer. The essence of voltage design of the lateral SJ is the design of the EVL surface field. (2)The essence of SAD(Substrate Assisted Depletion) effect and the reducing method of the SAD are revealed. The essence of the SAD is that the EVL can't provide the ideal uniform field boundary of the surface SJ layer, so that the electric neutral condition can't be satisfied, then the N/P pillars'charge balance is destroyed and the breakdown voltage is decreased.The EVL produce a uniform surface electric field by reducing the SAD.(3)The new structure which the line thin junction compensation layer SJ-LDMOS based on SOI is proposed.The new structure can eliminate the SAD and realize ENDIF(Enhanced Dielectric layer Field) effect. The chip will be test to base on the above model and the technology in project.

本项目基于SOI横向SJ-LDMOS引入等效耐压层(EVL)概念，将电荷补偿层与介质埋层看作EVL，凭借对横向SJ模型与技术的创新性研究，使得横向SJ耐压能力与纵向SJ类似。创新点有3个：(1)建立EVL模型，剖析横向SJ耐压机理：在器件漂移区求解3D泊松方程，得到表面场级数解及N/P条中线电场简化式，并求解具有任意掺杂电荷补偿层EVL表面场分布进而得到优化掺杂,其实横向SJ耐压设计本质就是对EVL表面场分布的设计。 (2)揭示衬底辅助耗尽效应(SAD)物理本质及降低途经，SAD本质是 EVL不能提供表面SJ层理想均匀场边界，其电中性条件不能满足，破坏N/P条电荷平衡，器件耐压降低。所以降低SAD就是使EVL产生均匀表面电场。(3)提出SOI基线性浅结优化补偿层SJ-LDMOS新结构。新器件消除SAD效应，实现埋氧层介质场增强(ENDIF)效果，本项目将根据上述模型及技术对新器件流片验证。

现代电力电子技术的发展要求功率器件具有更优越的高压、高速、低功耗性能，超结（Superjunction，简称SJ）器件作为一类新型功率器件能进一步提高器件的耐压，降低比导通电阻。SOI SJ LDMOS打破“硅极限”，缓解了BV和Ron,sp之间的矛盾，但SJ应用于横向功率器件时由于衬底辅助耗尽效应(Substrate Assisted Depletion, SAD)造成PN条电荷不平衡，耐压较低。本项目在基于SOI横向SJ LDMOS中引入等效耐压层(EVL)概念，将电荷补偿层与介质埋层看作EVL，凭借对横向SJ模型与技术的创新性研究，使得横向SJ耐压能力与纵向SJ类似。首先建立横向超结器件等效耐压层模型。将除超结之外的耐压层结构，即电荷补偿层与衬底视为等效耐压层，研究其整体电场对表面超结的调制，揭示衬底辅助耗尽效应的本质是衬底电离电荷影响表面超结电荷平衡，使得P条非全耗尽而N条全耗尽，器件耐压降低。从而得到理想衬底条件：电中性条件与均匀场条件。满足理想衬底条件时，横向超结器件可实现与纵向超结可比拟的器件耐压。然后提出SOI基线性浅结优化补偿层SJ LDMOS新结构TSL SOI SJ nLDMOS。在横向SJ等效耐压层(EVL)概念的指导下，实验获得两种薄硅层横向器件结构：1) TSL SOI LDMOS，流片中采用1.5µm的tS，3µm的tI的SOI材料，且顶层硅和衬底均为P型，SOI层电阻率为20Ω•cm，晶向100，器件工艺联合仿真的器件耐压为656V。实验中对TSL SOI的关键注入剂量进行拉偏，实验测试器件的最高耐压为694V。2) SJ TSL SOI LDMOS，其近源端和漏端分别采用1和0.15 μm的厚硅层和薄硅层结构，厚硅层区三次注入形成表面超结。该器件结合超结低Ron,sp与薄硅层结构的高临界场高VB优点，实现最高耐压为977 V的SOI高压器件结构，比导通电阻比全薄层结构降低34.8%，新结构硅层临界场达106.7 V/μm，验证了报告中提出的临界场公式。