相变材料应变工程与锗多栅晶体管的优化集成方案

The miniaturization of Silicon (Si) complementary metal-oxide-semiconductor (CMOS) field-effect transistors increases the packing density in integrated circuits but also introduces several challenges like mobility degradation and increased off-state leakage. Further enhancement of the Si metal-oxide-semiconductor field-effect transistor (MOSFET) performance is increasingly difficult due to the limitation of conventional device scaling. There is a strong need to explore new technologies, materials, or device structures to increase the transistor drive current and speed at a reduced supply voltage. Germanium (Ge) is considered as one of the most promising channel materials to replace silicon (Si) in future technology nodes due to its high electron and hole mobilities. Since 22 nm technology node, transistors with multi-gate structures (MuGFETs) have been used for high volume CMOS production since the 3-dimensional (3-D) gate geometry for the extremely scaled devices could improve the device electrostatics. High mobility Ge channel MuGFETs are promising device candidates for sub-10 nm high performance logic applications. To further boost the device performance, strain engineering could be adopted on Ge MuGFETs. Liner stressor has been used by the industry since 90 nm technology node. Recently, novel phase-change liner stressors, such as Ge2Sb2Te5 (GST) has been demonstrated to achieve more than 100% mobility enhancement for Ge p-channel MuGFETs. However, the study on strained Ge MuGFETs or even planar transistors is very limited. In this project, a 3-dimensional (3D) model will be established to study the mechanism for the strain induction. Experimental calibration will be performed on the model so as to obtain accurate channel strain profiles. Furthermore, the valence band structure in the inversion layer of the strained channel will be calculated. Hole mobility will then be estimated with channel scattering also taken into the consideration. By adjusting the structural parameters of the strain model and the thermal expansion rate of the phase-change materials, the channel strain profiles will change which will consequently change the valence band structure and hole mobility. An optimization of the phase-change liner stressor integrated with Ge MuGFETs will be provided based on the model adjustment so as to achieve the largest mobility enhancement.

硅器件的持续微型化降低了器件的生产成本，同时也引入了迁移率降低等问题。通过微细化的方法进一步提高硅MOSFET的性能已经非常困难了。锗同时具有很高的电子和空穴迁移率，因而被认为是替代硅作为器件沟道材料的理想选择之一。因此，锗沟道多栅器件（MuGFETs）很可能在10 nm以下高性能逻辑电路中被采用。应变工程之一的应变层（liner stressor）技术从90 nm节点开始已经被工业界采用以提高器件性能。但是liner stressor在锗MuGFET甚至平面器件上的研究却非常缺乏。本研究通过建立有实验校准的三维应变模型来学习相变材料应变层引起沟道应变的原理。有应变的反层价带模型和散射模型也会建立，用来准确评估应变锗器件的空穴迁移率。本研究通过调整应变模型的参量，进而推算锗器件的空穴迁移率的变化，来提供一个有相变材料应变层的锗MuGFET的优化制备方案，用以最大程度的提高器件的有效迁移率。

随着器件尺寸的逐渐减小，进一步通过简单的工艺步骤提升器件性能，从而完成摩尔定律对于器件性能的要求，已经变得极度困难。传统的平面Si器件无论是在成本上还是物理原理上，都面临着极大的挑战。在这种情况下，通过应变工艺，改变能带结构来进一步提升MOSFET器件的电学特性，是一个工艺简单且行之有效的方法。应变工程之一的应变层（liner stressor）技术从90 nm节点开始已经被工业界采用以提高器件性能。但是liner stressor在锗MuGFET甚至平面器件上的研究却非常缺乏。基于相变材料应变层对极度微缩化的逻辑器件在性能提升方面的巨大潜力，本项目对不同相变材料在Si，Ge基衬底以及器件进行集成并分析研究其对载流子迁移率以及器件性能所带来的影响。通过对比分析不同的器件结构，不同的材料组分对沟道应变的变化，建立准确的有限元应变模拟及迁移率计算模型，在实验以及模拟结合的情况下，本课题顺利分析获得了针对三维Ge基器件结合相变材料应变层技术的工艺优化方案，对亚10 nm以下小器件的性能提升，提供了行之有效的方案。