单器件存储器的性能机制研究和等效电路建模以及瞬态DOS表征建模

With the scaling along the Moore’s Law slowing down and the dimension of device approaching the physical limitations for acceptable electrical performance, it is needed to further improve transistors and memory cells. A simplified structure of memory is proposed in this project, using a single transistor to realize the memory function. The performance of the memory device after programming and erasing is also presented here. Further investigation such as the working mechanism and equivalent circuit modeling are scheduled and performed during the project. Meanwhile, amorphous oxide (AO) devices have attracted extensive attention due to the special properties such as room temperature processing conditions and transparency. They replace amorphous silicon (a-Si) Thin film transistors (TFTs) and have been applied in circuits such as liquid crystal displays. However, their properties still need improvement. Therefore, the investigation of transient characterization and modeling for their key electrical proertes such as subgap density of states (DOS) are needed for further study and better control of the devices. Nowadays, the methods for DOS in AO mainly use the measurements for a-Si involving photon, temperature or numerical calculations. In this project, the pure electrical transient measurement platform, without photon, temperature and a lot of mathematics is built up and employed for AO DOS characterization and modeling. In this way, the simulation tools for AO could be improved and used to predict the device electrical behaviors. The characterization and modeling study for the transient properties of device, and the investigation of physical mechanism and circuit modeling for the one transistor memory, can provide fundamental and guideline for the further development and application of key semiconductor devices.

随着摩尔定律放缓，工艺接近极限，要求存储器等半导体重要器件的进一步发展。本项目提出单晶体管存储器，目前已经实现了读写功能，将深入进行工作机制建模和等效电路研究。同时，非晶氧化物(amorphous oxide, AO)器件由于室温生长、透明等优点成为研究热点，正取代非晶硅薄膜晶体管被应用于液晶显示器等。但其性能亟待提高，有必要对其特性作深入研究。其特征参数如能级间有效态密度(Subgap Density of States, DOS)的瞬态表征建模亟待研究，一方面DOS是影响器件特性的关键参数，另一方面以往表征方法多沿用非晶硅的加光加温测试或者加入很多假设计算的电学测试。本项目将用纯电学的瞬态测试作DOS的定量表征与建模，搭建适用于AO器件的模拟平台，以预测和指导器件的性能改进。对器件瞬态特性测试建模，以及对单器件存储器的物理机制和等效电路原型的探讨，将为器件的优化发展与应用提供理论基础。

动态随机存储器（Dynamic Random Access Memory, DRAM）是SoC(System on Chip)设计的重要IP，存储阵列占存储芯片大部分面积，因此存储单元的优劣直接影响存储芯片的性能。随着摩尔定律放缓，工艺接近极限，要求存储器等半导体重要器件的进一步发展。项目负责人提出了“通过减小晶体管数目减小电路基本单元（门电路和存储器等）的面积”的创新思想，率先发表在2012年Nano Letters上，近两年来国际上有课题组在Nature Nanotechnology和IEDM上进行类似的研究报道。以此为基础，本项目提出了一个比较简单的存储器结构。在NSFC资助下，7篇SCI相关文章已发表，以此为基础，申请到2017年开始的浙江省杰出青年项目(编号 LR17F040002，关于非晶氧化物门电路和存储器的机理研究)，2019年开始的中科院装备项目(编号YJKYYQ20180021，关于瞬态缺陷表征平台的搭建)。本项目提出单晶体管存储器代替原有一个晶体管和一个电容的DRAM存储器，在130 nm工艺线进行了流片验证、经浙江省电子信息产品检验研究所第三方认证目前实现了读擦写功能、进行了工作机制建模研究，并进一步提出了“存算一体化单晶体管“的结构。单晶体管存储器也在实验室用柔性材料非晶氧化物(amorphous oxide, AO)材料实现。AO器件由于可低温生长、透明等优点成为研究热点，被应用于液晶显示器等。但其性能亟待提高，有必要对其特性作深入研究。其特征参数如能级间有效态密度(Subgap Density of States, DOS)的瞬态表征建模亟待研究，一方面DOS是影响器件特性的关键参数，另一方面以往表征方法多沿用非晶硅的加光加温测试或者加入很多假设计算的电学测试。本项目用磁控溅射等方法制备出性能稳定的柔性AO器件，用纯电学的瞬态测试作DOS的定量表征与建模，旨在搭建适用于AO器件的模拟平台，以预测和指导器件的性能改进。获得具有自主知识产权的瞬态DOS测试发明专利授权，运用温度等可变电学测量探针台，结合可原位瞬态缺陷电学测试，深入理解存算一体化单晶体管器件的微观工作机制。该研究有助于我国解决集成电路核心部件“卡脖子”的关键问题、有效延缓摩尔定律减小电路面积速度放缓的瓶颈。