低噪声无电感小数频率综合器研究与设计

Fractional-N frequency synthesizer is one of the most important circuit blocks in various wireless transceiver ICs. It provides a low phase noise clock signal, that with fine frequency resolution, to up-converter and down-convert the wanted signals..Due to the tradeoff between phase noise performance and power consumption of a voltage-controlled oscillator (VCO), frequency synthesizer also has a stringent tradeoff between its integrated jitter and dissipated power. Thus, it is the poor phase performance makes ring oscillator (RO) rarely adopted in high performance applications such as wireless communication ICs. While consider that RO has wider tuning range and much smaller die area compared to its LC counterpart, as well as naturally provides multiphase output, and is less suffered from on-chip magnetic couplings, it’s encouraging to implement high performance fractional-N frequency synthesizers with LC VCOs replaced by ROs. And this is exactly the motivation of this proposal..This project proposes a concept of phase rotating digital-to-time converter (DTC) based on sub-harmonic injection-locked RO, and it is proposing to introduce a finite impulse response filtering (FIR) block at the DTC’s output, which will be followed by a further frequency multiplication stage also based on RO. The analysis and simulation results shows the proposed inductor-less fractional-N synthesizer architecture achieves a performance comparable to state-of-the-art designs based on LC VCO.

小数型频率综合器是各类无线收发机芯片中最重要的电路模块之一。它产生一个频率精细可调的低噪声时钟信号，用于实现有用信号的上下变频。.受压控振荡器需要在噪声性能和功耗间折中的影响，频率综合器往往也无法兼顾其积分抖动性能和功耗。所以，相位噪声性能较差的环形振荡器极少被应用于诸如无线通信等对噪声性能要求苛刻的场合。但是考虑到环形振荡器较之电容电感谐振式振荡器拥有诸多优势，如：更宽的频率调谐范围、所占用芯片面积极小、天然具有多相位输出以及受电磁干扰较小等，使用环形振荡器代替电容电感谐振式振荡器实现高性能的小数频率综合器，是十分的具有吸引力的，这也正是本课题拟解决的问题。.本项目提出了一种具有倍频能力的相位循环式数字时间转换器，并拟在其后级实现有限冲激单位响应滤波环节和基于环形振荡器的进一步倍频。相关的分析和仿真结果表明提出的结构可以达到与基于电容电感谐振式振荡器的先进小数频率综合器类似的性能。

本项目主要研究现代片上系统中最重要的电路之一，频率综合电路，以期突破高性能设计对片上电感的依赖。在采用注入锁定、相位循环技术和高速和差调制器（DSM）方案，充分抑制了环形振荡器的相位噪声和量化噪声后，最终实现了一种超宽带的设计。. 在65nm CMOS上实现的设计，具有390-640MHz的频率调谐范围，其频率分辨率为0.23kHz、量化噪声为-120dBc/Hz@20MHz。在深入研究了其非线性、非理想性后，提出并分析了完整的级联结构。此外，还提出了一种混合式FIR滤波器来抑制带外相位噪声或量化噪声，以扩大此设计的应用范围。测试、分析及仿真结果表明，在某些情况下，无电感设计可达到类似基于电感设计的性能，从而大大节省电路成本。与传统的数字时间转换器（DTC）相比，该方案的优势是无需校准。. 本项目所得出的结论与电路，无论是作为低噪声小数倍频的时钟倍乘电路IP，还是作为级联锁相环的第一级以将小数锁相环设计简为整数设计，都十分具有应用前景，它的低成本的特性将非常受工业设计者的青睐。