低功耗低电源∑ΔA/D变换器研究设计与综合

Oversampled ADCs based on sigma-delta (SD) modulation are well-suited to the implementation of analog interfaces in digital communication and signal processing systems. These converters exploit the enhanced speed and circuit density of modern VLSI technologies and overcome limitations on resolution that result from the component mismatching. Now sigma-delta ADCs have been widely used for high resolution A/D conversion. In recent years, low power, wide band and high resolution ADCs implemented in CMOS technology are demanded due to the rapid development of wireless mobile communication and wide band internet access in order to improve the integration of the system and reduce cost. For example, the dynamic range of ADC used in RF receivers varies from larger than 80dB(for DECT) to larger than 100dB(for GSM). In xDSL (Digital Subscriber Line) system, the resolution of ADC varies from 12bits to 16bits according to its architecture. Oversampled ADC consists of modulator and decimation low pass filter, and its resolution and conversion speed are determined by the performance of the modulator, but its area and power consumption are mainly determined by the decimation low pass filter. The architectures and design methods of broadband sigma-delta modulators are studied, and based on it, the ways to optimize the circuit architecture, minimize the circuit nonidealities and improve the circuit performance are analyzed; The principles and design methods of the decimation filter are studied. Furthermore, the ways to optimize the circuit architecture and improve the circuit performance are analyzed and a number of design techniques are used to decrease the area and power consumption of the filter. Based on the above study, the corresponding circuits are designed..Two different architectures of sigma-delta modulators with 700KHz bandwidth and 14-bit resolution are designed using two different technologies. One modulator uses 2-1-1 multibit architecture with fully differential switched capacitor circuits, whose oversampling ratio is 16 and sampling frequency is 25MHz. It is implemented in the CSMC 0.6mm CMOS process with double-poly and double-metal. It operates under a single 3.3V supply and the output range of the quantizer is 2V. Simulation results show that the modulator achieves the resolution higher than 14bits and consumes about 76mW. Another modulator uses 2-1-1 single bit architecture with fully differential switched capacitor circuits, whose oversampling ratio is 32 and sampling frequency is 50MHz. It is implemented in the UMC 0.18mm CMOS process with single-poly and 6-metal. It operates under a single 3.3V supply and the output range of the quantizer is 2V. Simulation results show that the modulator achieves the resolution higher than 15bits and consumes about 90mW. An FIR decimation filter used in 14bit 1.5625MHz Nyquist rate oversampled ADC is designed. Considering the finite wordlengh effect of input signals, coefficients and intermediate results, simulation results shows that its passband is 700KHz, stopband is 862.5KHz, the ripple at 1KHz is 0.0005dB, the passband ripple is less than 0.02dB, and the stopband attenuation is larger than 86 dB.

本项目研究在3V+/-0。3电源电压条件下,达到14位精度以上的低功耗∑ΔA/D变换器和它的自动综合.关键是要解决低电源,低功耗下调制器中的OTA的动态范围,数字信号对模拟信号的串扰,建立低功耗∑ΔA/D的模型,并实现自动综合.