门电路复合应力模式下NBTI的退化机制及建模

Negative Bias Temperature Instability (NBTI) is one of the most significant transistor reliability impediment in nanometer device and circuit. It's difficult to describe the accurate physical mechanism of NBTI due to its sophisticated behaviors and various explanation of hypothesis. The lack of accurate NBTI aging model becomes the bottleneck of integrated circuit design in reliability. In this project, the research focuses will be casted on the NBTI aging characteristic of logic gate under compound stress, including its generation discipline, mechanism and degradation model. Considering the finite oxide thickness which may lead to three different boundary hypothesis including the reflective and the absorbent, the third one assumes that the H2/H would diffuse across the interface of SiO2/Poly-Si and deep into polysilicon. The reaction-diffusion (R-D) equation for the generation/passivation of the interface traps would be described, analyzed and numerical solved precisely. The distribution change of H2/H under various compound stress on the surface of Si/SiO2, inside SiO2 and polysilicion will be calculated and investigated. Therefore, the mathematic model for long term dynamic degradation of △Vth will be built up based on the solved results of R-D model. Consequently, the test circuits of aging will be designed using nanometer CMOS technology, in which the calibration and the modules to generate various compound stresses will also be embedded. Meanwhile, the UDRM model will be coded, compiled and integrated into Eldo simulator, and then the propagation delay change will be simulated using the UDRM model built up based on the solving of R-D model. In last, the NBTI degradation test platform will be setup, and the aging model of △Vth would be corrected and improved according to the △Tp degradation test which will be carried out under the control of different stress mode. In general, the main aim of this project is to research and investigate the behaviors and the physical mechanism of NBTI under various compound stresses, and then provide a precise NBTI degradation model.

负偏压温度不稳定性（NBTI）是制约纳米器件/电路性能及寿命的关键因素。其形成机理复杂，较难准确完整地表征。特别在应力多变的低功耗模式下，准确退化模型的缺失已成为制约纳米集成电路可靠性设计的主要瓶颈。本项目以门电路复合应力模式下的NBTI退化特性为研究对象，对其退化规律、机制和数学建模进行研究。具体内容包括：数值求解三种不同SiO2/多晶硅栅界面边界条件下的反应扩散（R-D）方程，分析复合应力驱动模式下Si/SiO2界面、栅氧化层和多晶硅栅中H2/H连续扩散浓度分布变化规律；建立复合应力模式下长时动态△Vth退化数学模型；设计基于延迟单元的退化测试电路，并进行测试；编写UDRM函数并仿真延迟数据通道，对比仿真与测试，修正并完善本项目拟提出的△Vth退化数学模型。本项目旨在揭示多变应力模式下的NBTI退化规律及其形成机制，为纳米集成电路可靠性设计提供准确的NBTI退化模型。

负偏压温度不稳定性（NBTI）是制约纳米器件/电路性能及寿命的关键因素。其形成机理复杂，在应力多变的低功耗模式下，准确退化模型的缺失已成为制约纳米集成电路可靠性设计的主要瓶颈，是国内外该领域的研究热点。本项目以门电路复合应力模式下的NBTI 退化特性为研究对象，对其退化规律、机制和数学建模进行研究。课题组具体研究内容包括：1）基于国内华力40纳米CMOS平面工艺，进行了延迟测试单元的电路设计、仿真、版图实现和流片，为获取40纳米工艺NBTI退化数据奠定了基础，申请发明专利2项；2）设计了两种测试平台，包括Labview测试平台和FPGA的测试平台，并进行了调试实现；3）对两种不同尺寸单PMOS管（9um/9um，0.9um/0.036um）进行了测试（Vstr=1.8V和2.3V，温度T=85度和125度）；4）基于本课题组所设计的测试电路进行测试，获得了相应的测试数据，并与单管测试数据进行了比对；5）提出了Coarse+Fine的模型参数提取方法，粗提取采用坐标线性变换，确定参数变化范围，再进一步利用遗传算法进行参数精提取，同时开发相应的参数提取软件（基于Matlab），申请发明专利1项；6）从理论角度着手，提出复合应力模式（DVFS）下的NBTI退化模型，对原有传统模型进行了修正，使得修正后模型可精确跟踪电路在DVFS模式下的退化过程，并在IEEE Transaction DMR上发表SCI论文1篇；7）对逻辑门电路退化进行理论分析，并提出了基本逻辑门电路的退化依赖关系表达式，为门级电路退化的描述提供了理论基础。本项目旨在揭示了多变应力模式下的 NBTI 退化规律，为纳米集成电路可靠性设计提供准确的 NBTI 退化模型。